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S71WS-Nx0 Based MCPs
Stacked Multi-Chip Product (MCP)
128/256/512 Megabit (32M/16M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with pSRAM Type 4
Data Sheet
ADVANCE INFORMATION
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71WS-N_01
Revision A
Amendment 4
Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Advance
Information
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
S71WS-Nx0 Based MCPs
Stacked Multi-Chip Product (MCP)
128/256/512 Megabit (32M/16M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with pSRAM Type 4
ADVANCE INFORMATION
General Description
The S71WS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: One or more flash memory die pSRAM Type 4--Compatible pSRAM The products covered by this document are listed in the table below. For details about their specifications, please refer to the individual constituent datasheet for further details.
Device S71WS512ND0 S71WS256ND0 S71WS256NC0 S71WS128NC0 Flash Density 512 Mb 256 Mb 128 Mb 64 Mb 128 Mb pSRAM Density 64 Mb 32 Mb 16 Mb
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 V to 1.95 V Burst Speed: 54 MHz, 66 MHz Package -- 8 x 11.6 mm, 9 x 12 mm Operating Temperature -- Wireless, -25 C to +85 C
Publication Number S71WS-N_01
Revision A
Amendment 4
Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Advance
Information
Contents
S71WS-Nx0 Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 2 3 4 5 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Connection Diagrams/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Special Handling Instructions for FBGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.2 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 1.8 V RAM Type 4 - Based Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 Look-Ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.3 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.1 TLA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm. . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.2 TSD084--84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . .18 5.3.3 FEA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm . . . . . . . . . . . . . . . . . . . . . . . .19
S29WS-N MirrorBitTM Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 7 8 9
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.3 Synchronous (Burst) Read Mode & Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.3.4 Continuous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3.5 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3.6 8-, 16-, 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3.7 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.5.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.5.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.5.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.5.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.5.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.5.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.6 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2 S71WS-Nx0 Based MCPs S71WS-N_01_A4 September 15, 2005
Advance
Information
12
13
14
15 16
1.8V pSRAM Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
17 18 19 20 21 22 23
11.6.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.4 Write Pulse "Glitch Protection" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.1 Factory Secured SiliconSector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.8.4 AC Characteristics--Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 15.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Power Up and Standby Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 20.1 Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 20.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Mode Register Setting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 22.1 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 22.2 Mode Register Setting Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23.1 Asynchronous 4 Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23.3 Asynchronous Write Operation in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Synchronous Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 24.1 Synchronous Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 24.2 Synchronous Burst Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Synchronous Burst Operation Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 25.1 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 25.2 Latency Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 25.3 Burst Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 S71WS-Nx0 Based MCPs 3
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1.8V pSRAM Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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25.4 Burst Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 25.5 Wait Control (WAIT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 25.6 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low Power Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 26.7 Partial Array Refresh (PAR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.8 Driver Strength Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 26.1 Internal TCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Capacitance (Ta = 25C, f = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 30.1 Common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 31.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 31.2 Asynchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 31.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 31.3.1 Asynchronous Read Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 31.3.2 Asynchronous Write Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 31.3.3 Asynchronous Write Timing Waveform in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 31.3.4 Asynchronous Write Timing Waveform in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 32.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 32.2 Synchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 32.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 32.3.1 Synchronous Burst Operation Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 32.3.2 Synchronous Burst Read Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 32.3.3 Synchronous Burst Read Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 32.3.4 Synchronous Burst Write Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 32.3.5 Synchronous Burst Read Suspend Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Transition Timing Waveform Between Read And Write . . . . . . . . . . . . . . . . . . . . . . . . . . 139
34 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 35 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 36 Power Up and Standby Mode Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 36.1 Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 36.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 37 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 38 Mode Register Setting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 38.1 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 38.2 MRS Pin Control Type Mode Register Setting Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 39 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 39.1 Asynchronous 4 Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 39.2 Asynchronous Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 39.3 Asynchronous Write Operation in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 40 Synchronous Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 40.1 Synchronous Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 40.2 Synchronous Burst Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 41 Synchronous Burst Operation Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.1 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.2 Latency Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.3 Burst Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 41.4 Burst Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 41.5 Wait Control (WAIT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 41.6 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
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42 Low Power Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 42.1 Internal TCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 42.2 Driver Strength Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 42.3 Partial Array Refresh (PAR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 43 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 44 DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 45 Capacitance (Ta = 25C, f = 1 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 46 DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 46.1 Common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 47 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 47.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 47.2 Asynchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 47.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 47.3.1 Asynchronous Read Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 47.3.2 Asynchronous Write Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 47.3.1 Asynchronous Write Timing Waveform in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 48 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 48.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 48.2 Synchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 48.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 48.3.1 Synchronous Burst Operation Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 48.3.2 Synchronous Burst Read Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 48.3.3 Synchronous Burst Read Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 48.3.4 Synchronous Burst Write Stop Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 48.3.5 Synchronous Burst Read Suspend Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 49 Transition Timing Waveform Between Read And Write . . . . . . . . . . . . . . . . . . . . . . . . . . 180 50 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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Information
Tables
Table 3.1 Table 6.1 Table 9.1 Table 9.2 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 S29WS256N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 S29WS128N Sector & Memory Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Address Latency (S29WS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Address Latency (S29WS128N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Address/Boundary Crossing Latency (S29WS256N @ 80MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Address/Boundary Crossing Latency (S29WS256N @ 54MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Address/Boundary Crossing Latency (S29WS128N). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10.10 Autoselect Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10.11 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10.12 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10.13 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10.14 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 10.15 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 10.16 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 10.17 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 10.18 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 10.19 Software Functions and Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 10.20 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 10.21 Reset LLD Function = lld_ResetCmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 11.1 Table 11.2 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 14.1 Table 14.2 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 21.1 Table 21.2 Table 21.3 Table 22.1 Table 22.2 Table 22.3 Table 25.1 Table 25.2 Table 25.3 Table 26.1 Table 31.1 Table 31.2 Table 31.3 Table 31.4 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0). . . . . . . . . . . . . . . . . . . . . . . . 106 Mode Register Setting According to Field of Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Mode Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 MRS AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Latency Count Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Number of CLocks for 1st Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 PAR Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Asynchronous Page Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Asynchronous Write AC Characteristics (UB# & LB# Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Advance
Information
Table 31.5 Table 31.6 Table 31.7 Table 31.8 Table 31.9 Table 32.1 Table 32.2 Table 32.3 Table 32.4 Table 32.5 Table 32.6 Table 32.7 Table 32.8 Table 32.9 Table 33.1 Table 33.2 Table 33.3 Table 33.4 Table 33.5 Table 33.6 Table 37.1 Table 37.2 Table 37.3 Table 38.1 Table 38.2 Table 38.3 Table 41.1 Table 41.2 Table 41.3 Table 42.1 Table 47.1 Table 47.2 Table 47.3 Table 47.4 Table 47.5 Table 47.6 Table 47.7 Table 47.8 Table 48.1 Table 48.2 Table 48.3 Table 48.4 Table 48.5 Table 48.6 Table 48.7 Table 48.8 Table 48.9 Table 49.1 Table 49.2 Table 49.3 Table 49.4 Table 49.5 Table 49.6
Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Burst Operation AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Burst Read Stop AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Burst Write Stop AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Burst Read Suspend AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 139 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 141 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0) . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0). . . . . . . . . . . . . . . . . . . . . . . . 149 Mode Register Setting According to Field of Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Mode Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 MRS AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Latency Count Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Number of CLocks for 1st Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 PAR Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Asynchronous Page Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Asynchronous Write AC Characteristics (UB# & LB# Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Asynchronous Write in Synchronous Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Burst Operation AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Burst Read Stop AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Burst Write Stop AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Burst Read Suspend AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 180 Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 182 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 185
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
7
Advance
Information
Figures
Figure 7.1 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 11.1 Figure 11.2 Figure 11.3 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 S29WS-N Block Diagram....................................................................................................................22 Synchronous/Asynchronous State Diagram...........................................................................................27 Synchronous Read ............................................................................................................................29 Single Word Program.........................................................................................................................35 Write Buffer Programming Operation ...................................................................................................39 Sector Erase Operation ......................................................................................................................41 Write Operation Status Flowchart ........................................................................................................48 Advanced Sector Protection/Unprotection .............................................................................................55 PPB Program/Erase Algorithm .............................................................................................................58 Lock Register Program Algorithm.........................................................................................................61 Maximum Negative Overshoot Waveform .............................................................................................68 Maximum Positive Overshoot Waveform ...............................................................................................68 Test Setup .......................................................................................................................................69 Input Waveforms and Measurement Levels ...........................................................................................70 VCC Power-up Diagram ......................................................................................................................70 CLK Characterization .........................................................................................................................72 CLK Synchronous Burst Mode Read......................................................................................................74 8-word Linear Burst with Wrap Around.................................................................................................75 8-word Linear Burst without Wrap Around ............................................................................................75
Figure 14.10 Linear Burst with RDY Set One Cycle Before Data ..................................................................................76 Figure 14.11 Asynchronous Mode Read...................................................................................................................77 Figure 14.12 Reset Timings...................................................................................................................................78 Figure 14.13 Chip/Sector Erase Operation Timings ...................................................................................................80 Figure 14.14 Program Operation Timing Using AVD# ................................................................................................81 Figure 14.15 Program Operation Timing Using CLK in Relationship to AVD#.................................................................82 Figure 14.16 Accelerated Unlock Bypass Programming Timing ...................................................................................83 Figure 14.17 Data# Polling Timings (During Embedded Algorithm) .............................................................................83 Figure 14.18 Toggle Bit Timings (During Embedded Algorithm) ..................................................................................84 Figure 14.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................84 Figure 14.20 DQ2 vs. DQ6 ....................................................................................................................................85 Figure 14.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................85 Figure 14.22 Latency with Boundary Crossing into Program/Erase Bank ......................................................................86 Figure 14.23 Example of Wait States Insertion ........................................................................................................87 Figure 14.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................88 Figure 20.1 Figure 20.2 Figure 22.1 Figure 22.2 Figure 23.1 Figure 23.2 Figure 24.1 Figure 24.2 Figure 25.1 Figure 25.2 Figure 26.1 Figure 31.1 Figure 31.2 Figure 31.3 Figure 31.4 Figure 31.5 Figure 31.6 Figure 31.7 Figure 31.8 Figure 31.9 Power Up Timing............................................................................................................................. 104 Standby Mode State Machines .......................................................................................................... 104 Pin MRS Timing Waveform (OE# = VIH) ............................................................................................. 108 Software MRS Timing Waveform ....................................................................................................... 109 Asynchronous 4-Page Read .............................................................................................................. 110 Asynchronous Write......................................................................................................................... 110 Synchronous Burst Read .................................................................................................................. 111 Synchronous Burst Write.................................................................................................................. 111 Latency Configuration (Read)............................................................................................................ 112 WAIT# and Read/Write Latency Control ............................................................................................. 113 PAR Mode Execution and Exit............................................................................................................ 115 PAR Mode Execution and Exit............................................................................................................ 117 Timing Waveform Of Asynchronous Read Cycle ................................................................................... 119 Timing Waveform Of Page Read Cycle................................................................................................ 120 Timing Waveform Of Write Cycle ....................................................................................................... 121 Timing Waveform of Write Cycle(2) ................................................................................................... 122 Timing Waveform Of Write Cycle (Address Latch Type) ........................................................................ 123 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 124 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 125 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 126
8
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Advance
Information
Figure 31.10 Timing Waveform Of Multiple Write Cycle (Low ADV# Type).................................................................. 127 Figure 32.1 Figure 32.2 Figure 32.3 Figure 32.4 Figure 32.5 Figure 32.6 Figure 32.7 Figure 32.8 Figure 32.9 Figure 33.1 Figure 33.2 Figure 33.3 Figure 33.4 Figure 33.5 Figure 33.6 Figure 36.1 Figure 36.2 Figure 38.1 Figure 39.1 Figure 39.2 Figure 40.1 Figure 40.2 Figure 41.1 Figure 41.2 Figure 42.1 Figure 47.1 Figure 47.2 Figure 47.3 Figure 47.4 Figure 47.5 Figure 47.6 Figure 47.7 Figure 47.8 Figure 47.9 Figure 48.1 Figure 48.2 Figure 48.3 Figure 48.4 Figure 48.5 Figure 48.6 Figure 48.7 Figure 48.8 Figure 48.9 Figure 49.1 Figure 49.2 Figure 49.3 Figure 49.4 Figure 49.5 Figure 49.6 AC Output Load Circuit..................................................................................................................... 128 Timing Waveform Of Basic Burst Operation......................................................................................... 130 Timing Waveform of Burst Read Cycle (1) .......................................................................................... 131 Timing Waveform of Burst Read Cycle (2) .......................................................................................... 132 Timing Waveform of Burst Read Cycle (3) .......................................................................................... 133 Timing Waveform of Burst Write Cycle (1) .......................................................................................... 134 Timing Waveform of Burst Write Cycle (2) .......................................................................................... 135 Timing Waveform of Burst Read Stop by CS# ..................................................................................... 136 Timing Waveform of Burst Write Stop by CS# ..................................................................................... 137 Synchronous Burst Read to Asynchronous Write (Address Latch Type) ................................................... 139 Synchronous Burst Read to Asynchronous Write (Low ADV# Type) ........................................................ 140 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing ......................................... 141 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing .............................................. 142 Synchronous Burst Read to Synchronous Burst Write Timing................................................................. 143 Synchronous Burst Write to Synchronous Burst Read Timing................................................................. 144 Power Up Timing............................................................................................................................. 147 Standby Mode State Machines .......................................................................................................... 147 Mode Register Setting Timing (OE# = VIH) ......................................................................................... 151 Asynchronous 4-Page Read .............................................................................................................. 152 Asynchronous Write......................................................................................................................... 152 Synchronous Burst Read .................................................................................................................. 153 Synchronous Burst Write.................................................................................................................. 153 Latency Configuration (Read)............................................................................................................ 154 WAIT# and Read/Write Latency Control ............................................................................................. 155 PAR Mode Execution and Exit............................................................................................................ 157 PAR Mode Execution and Exit............................................................................................................ 159 Timing Waveform Of Asynchronous Read Cycle ................................................................................... 161 Timing Waveform Of Page Read Cycle................................................................................................ 162 Timing Waveform Of Write Cycle ....................................................................................................... 163 Timing Waveform of Write Cycle(2) ................................................................................................... 164 Timing Waveform Of Write Cycle (Address Latch Type) ........................................................................ 165 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 166 Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 167 Timing Waveform Of Multiple Write Cycle (Low ADV# Type).................................................................. 168 AC Output Load Circuit..................................................................................................................... 169 Timing Waveform Of Basic Burst Operation......................................................................................... 171 Timing Waveform of Burst Read Cycle (1) .......................................................................................... 172 Timing Waveform of Burst Read Cycle (2) .......................................................................................... 173 Timing Waveform of Burst Read Cycle (3) .......................................................................................... 174 Timing Waveform of Burst Write Cycle (1) .......................................................................................... 175 Timing Waveform of Burst Write Cycle (2) .......................................................................................... 176 Timing Waveform of Burst Read Stop by CS# ..................................................................................... 177 Timing Waveform of Burst Write Stop by CS# ..................................................................................... 178 Synchronous Burst Read to Asynchronous Write (Address Latch Type) ................................................... 180 Synchronous Burst Read to Asynchronous Write (Low ADV# Type) ........................................................ 181 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing ......................................... 182 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing .............................................. 183 Synchronous Burst Read to Synchronous Burst Write Timing................................................................. 184 Synchronous Burst Write to Synchronous Burst Read Timing................................................................. 185
Figure 32.10 Timing Waveform of Burst Read Suspend Cycle (1).............................................................................. 138
Figure 48.10 Timing Waveform of Burst Read Suspend Cycle (1).............................................................................. 179
September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
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Information
1
Product Selector Guide
Device Model Numbers A3 S71WS256NC0 A7 A2 A6 Y3 S71WS256ND0 Y7 Y2 Y6 E3 S71WS512ND0 E7 E2 E6 A3 S71WS128NC0 A7 A2 A6 WS128N 64 66 66 WS512N 128 66 66 WS256N 54 128 66 66 54 64 66 66 Flash pSRAM Density (Mb) Flash Speed (MHz) 54 pSRAM Speed (MHz) 54 DYB Power-Up State (See Note) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 11.6x8.0x1.2 1.8V RAM Type 4 9x12x1.2 11.6x8.0x1.2 pSRAM Supplier Package (mm)
54
54
9x12x1.4
54
54
Note: 0 (Protected), 1 (Unprotected [Default State])
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Information
2
Ordering Information
The ordering part number is formed by a valid combination of the following:
S71WS 256 N C 0 BA W A 3 0 Packing Type 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel RAM 3 7 2 6 Supplier, DYB Power Up, Speed Combinations = RAM Type 4, 0, 54 MHz = RAM Type 4, 1, 54 MHz = RAM Type 4, 0, 66 MHz = RAM Type 4, 1, 66 MHz Modifier 1.2 mm, 8 x 11.6, 84-ball FBGA 1.2 mm, 9 x 12, 84-ball FBGA 1.4 mm, 9 x 12, 84-ball FBGA
Package A = E = Y =
Temperature Range W = Wireless (-25C to +85C) Package Type BA = Very Thin Fine-Pitch BGA Lead (Pb)-free Compliant Package BF = Very Thin Fine-Pitch BGA Lead (Pb)-free Package Chip Contents--2 No content pSRAM Density C = 64 Mb D = 128 Mb Process Technology N = 110nm MirrorBitTM Technology Flash Density 512 = 512Mb (2x256Mb) 256 = 256Mb Device Family S71WS= Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode Flash Memory + xRAM
Valid Combinations S71WS128N S71WS256N S71WS512N C D C D 0 BA, BF W A E A Y E 2, 6, 3, 7 3, 7 2, 6, 3, 7 2, 6 2, 6, 3, 7
Package Marking Note: The package marking omits the leading S from the ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
September 15, 2005 S71WS-N_01_A4
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Information
3
Input/Output Descriptions
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1
Symbol A23-A0 DQ15-DQ0 OE# WE# VSS NC RDY CLK Address inputs Data input/output
Input/Output Descriptions
Description
Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Ground No Connect; not connected internally Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Chip-enable input for pSRAM. Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode. Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb MCP only. Mode register select for Type 4. Flash 1.8 Volt-only single power supply. pSRAM Power Supply. Upper Byte Control (pSRAM). Lower Byte Control (pSRAM) Do Not Use
AVD# F-RST# F-WP# F-ACC R-CE1# F1-CE# F2-CE# R-MRS F-VCC R-VCC R-UB# R-LB# DNU
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4
MCP Block Diagram
F-VCC Flash-only Address Shared Address CLK WP# ACC F1-CE# OE# WE# F-RST# AVD# F2-CE# R-VCC 22
(Note 1)
22
VCC
VID
(Note 1)
DQ15 to DQ0 CLK WP# ACC Flash 1 CE# (Note 3) Flash 2 OE# WE# RESET# RDY AVD#
16
DQ15 to DQ0
RDY VSS
VCC
VCCQ
R-CE1#
R-UB# R-LB# R-CE2
Notes:
1. 2. 3.
I/O15 to I/O0 CLK CE# WE# pSRAM OE# WAIT# UB# VSSQ LB# CE2 AVD#
16
For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash. Only needed for S71WS512N. For the 128M pSRAM devices, there are 23 shared addresses.
September 15, 2005 S71WS-N_01_A4
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Information
5
5.1
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71WS-N.
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time.
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S71WS-Nx0 Based MCPs
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5.2
Connection Diagrams
5.2.1 1.8 V RAM Type 4 - Based Pinout
84-ball Fine-Pitch Ball Grid Array Type 4-based Pinout (Top View, Balls Facing Down)
A1 DNU B2 AVD# C2 F-WP# D2 A3 E2 A2 F2 A1 G2 A0 H2 F1-CE# J2 R-CE1# K2 RFU L2 RFU M1 DNU B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 CLK C4 R-LB# D4 B5 F2-CE# C5 F-ACC D5 B6 RFU C6 WE# D6 RFU E6 A20 F6 A23 G6 RFU H6 DQ4 J6 R-VCC K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D9 A15 E9 A21 F9 A22 G9 A16 H9 R-MRS J9 VSS K9 RFU L9 RFU
A10 DNU
Legend
R-UB# F-RST# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU E5 RDY F5 RFU G5 RFU H5 DQ3 J5 F-VCC K5 DQ11 L5 F-VCC
Shared
Flash XIP only
RAM only
1st Flash Only
2nd Flash Only
Reserved for Future Use
M10 DNU
Notes:
1. 2. In MCPs based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCPs based on two S29WS256N (S71WS512), ball B5 is or F2-CE#. Addresses are shared between Flash and RAM depending on the density of the pSRAM. MCP S71WS128NC0 S71WS256NC0 S71WS512ND0 Flash-only Addresses A22 A23-A22 A23 Shared Addresses A21-A0 A21-A0 A22-A0
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Information
5.2.2
Look-Ahead Connection Diagram
A1 RFU
B1
A2
A9
A10
Legend: RFU
B2
RFU
B9
RFU
B10
X
RFU (Reserved for Future Use)
RFU
RFU
RFU
RFU
C2 AVD# D2 WP# E2 A3 F2 A2 G2
A1
C3 VSS D3 A7 E3 A6 F3 A5 G3
A4
C4 CLK D4 R-LB# D4 R-UB# F4 A18 G4
A17
C5 F2-CE# D5 ACC C7 F-RST# F5 RDY/WAIT# G5
R2-CE1
C6 F-VCC D6 WE# E6 R1-CE2 F6 A20 G6
A23
C7 F-CLK# D7 A8 E7 A19 F7 A9 G7
A10
C8 R-OE# D8 A11 E8 A12 F8 A13 G8
A14
C9 F2-OE# D9 F3-CE# E9 A15 F9 A21 G9
A22
X
Code Flash Only
X
MirrorBit Data Only
X
Flash/Data Shared
H2 A0 J2 F1-CE# K2 R1-CE1# L2 R-VCC M2 A27
H3 VSS J3 OE# K3 DQ0 L3 DQ8 M3 A26
H4 DQ1 J4 DQ9 K4 DQ10 L4 DQ2 M4 VSS
H5 R2-VCC J5 DQ3 K5 F-VCC L5 DQ11 M5 F-VCC
H6 R2-CE2 J6 DQ4 E6 R1-VCC L6 A25 M6 F4-CE#
H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 R-VCCQ
H8 A24 J8 DQ15 K8 DQ7 L8 DQ14 M8 F-VCCQ
H9 A16 J9 R-CRE or R-MRS K9 VSS L9 WP# M9 R-CLK#
N9 RFU P9 RFU
X
Flash/xRAM Shared
X
pSRAM Only
X
xRAM Shared
N1
F-DQS0 P1 RFU
N1
N2 RFU P2 RFU
N10
F-DQS1 P10 RFU
Notes:
1. 2. In a 3.0V system, the GL device used as Data has to have WP tied to VCC F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash
Ball D2 D5 F5
3.0 V VCC NC WP#/ACC RY/BY
1.8 V VCC F-WP# ACC F-RDY/R-WAIT#
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5.3
Physical Dimensions
5.3.1 TLA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6 x 8.0 x 1.2 mm
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
M CAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 TLA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10, E1,E10,F1,F10,G1,G10, H1,H10,J1,J10,K1,K10,L1,L10, M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
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5.3.2
TSD084--84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.2 mm
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
MCAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TSD 084 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.17 0.81 NOM ------12.00 BSC. 9.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.94 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10 E1,E10,F1,F10,G1,G10 H1,H10,J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3426\ 16-038.22
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Information
5.3.3
FEA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 x 1.4 mm
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
M CAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 FEA 084 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.10 1.11 NOM ------12.00 BSC. 9.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A2,A3,A4,A5,A6,A7,A8,A9 B1,B10,C1,C10,D1,D10 E1,E10,F1,F10,G1,G10 H1,H10,J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 0.45 MAX 1.40 --1.26 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3423 \ 16-038.21a
BSC is an ANSI standard for Basic Space Centering
September 15, 2005 S71WS-N_01_A4
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S29WS-N MirrorBitTM Flash Family
S29WS256N, S29WS128N 256/128 Megabit (16/8 M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory
ADVANCE INFORMATION
General Description
The Spansion S29WS256/128 are MirrorbitTM Flash products fabricated on 110-nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 80 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for today's demanding wireless applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70-1.95 V) 110 nm MirrorBitTM Technology Simultaneous Read/Write operation with zero latency 32-word Write Buffer Sixteen-bank architecture consisting of 16/8 Mwords for WS256N/128N, respectively Four 16 Kword sectors at both top and bottom of memory array 254/126 64 Kword sectors (WS256N/128N) Programmable linear (8/16/32) with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) RDY output indicates data available to system Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of top and bottom sectors Dual boot sector configuration (top and bottom) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings ACC input pin to reduce factory programming time Support for Common Flash Interface (CFI)
Performance Characteristics
Read Access Times
Speed Option (MHz) Max. Synch. Latency, ns (tIACC) Max. Synch. Burst Access, ns (tBACC) Max. Asynch. Access Time, ns (tACC) Max CE# Access Time, ns (tCE) Max OE# Access Time, ns (tOE) 80 80 9 80 80 13.5 66 80 11.2 80 80 13.5 54 80 13.5 80 80 13.5
Current Consumption (typical values)
Continuous Burst Read @ 80 MHz Simultaneous Operation (asynchronous) Program (asynchronous) Erase (asynchronous) Standby Mode (asynchronous) 38 mA 50 mA 19 mA 19 mA 20 A
Typical Program & Erase Times
Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VACC) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 40 s 9.4 s 6 s 150 ms 600 ms
Publication Number S71WS-N_01
Revision A
Amendment 4
Issue Date September 15, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
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Information
6
Input/Output Descriptions & Logic Symbol
Table 6.1 identifies the input and output package connections provided on the device.
Table 6.1
Symbol
A23-A0 DQ15-DQ0 CE# OE# WE# VCC VSS NC RDY CLK
Input/Output Descriptions
Description
Type
Input I/O Input Input Input Supply I/O No Connect Output Input
Address lines for WS256N (A22-A0 for WS128). Data input/output. Chip Enable. Asynchronous relative to CLK. Output Enable. Asynchronous relative to CLK. Write Enable. Device Power Supply. Ground. Not connected internally. Ready. Indicates when valid burst data is ready to be read. Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. Address Valid. Indicates to device that the valid address is present on the address inputs. When low during asynchronous mode, indicates valid address; when low during burst mode, causes starting address to be latched at the next active clock edge. When high, device ignores address inputs.
AVD#
Input
RESET# WP#
Input Input
Hardware Reset. Low = device resets and returns to reading array data. Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use (see MCP look-ahead pinout for use with MCP).
ACC RFU
Input Reserved
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Information
7
Block Diagram
VCC VSS
DQ15-DQ0 RDY Buffer RDY Erase Voltage Generator Input/Output Buffers
WE# RESET# WP# ACC
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic Data Latch
CE# OE#
Y-Decoder VCC Detector
Y-Gating
Address Latch
Timer
X-Decoder
Cell Matrix
AVD# CLK
Burst State Control
Burst Address Counter
Amax-A0*
* WS256N: A23-A0 WS128N: A22-A0
Figure 7.1
S29WS-N Block Diagram
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8
Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices Understanding Burst Mode Flash Memory Devices Simultaneous Read/Write vs. Erase Suspend/Resume MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read Design-In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers Enhanced Flash drivers Flash file system
CAD Modeling Support
VHDL and Verilog IBIS ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support: Email US and Canada: HW.support@amd.com Asia Pacific: asia.support@amd.com Europe, Middle East, and Africa Japan: http://edevice.fujitsu.com/jp/support/tech/#b7 Frequently Asked Questions (FAQ) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 Phone US: (408) 749-5703 Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited 4-33-4 Nishi Shinjuku, Shinjuku-ku Tokyo, 160-0023 Telephone: +81-3-5302-2200 Facsimile: +81-3-5302-2674 http://www.spansion.com
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9
Product Overview
The S29WS-N family consists of 256, 128 Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for today's wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 16 or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable.
9.1
Memory Map
The S29WS256/128N Mbit devices consist of 16 banks organized as shown in Table 9.1-Table 9.2.
Table 9.1
Bank Size Sector Count Sector Size (KB) Bank
S29WS256N Sector & Memory Address Map
Sector/ Sector Range
SA000 SA001
Address Range
000000h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 3F0000h-3FFFFFh 400000h-40FFFFh to 4F0000h-4FFFFFh 500000h-50FFFFh to 5F0000h-5FFFFFh 600000h-60FFFFh to 6F0000h-6FFFFFh 700000h-70FFFFh to 7F0000h-7FFFFFh 800000h-80FFFFh to 8F0000h-8FFFFFh 900000h-90FFFFh to 9F0000h-9FFFFFh A00000h-A0FFFFh to AF0000h-AFFFFFh B00000h-B0FFFFh to BF0000h-BFFFFFh C00000h-C0FFFFh to CF0000h-CFFFFFh D00000h-D0FFFFh to DF0000h-DFFFFFh E00000h-E0FFFFh to EF0000h-EFFFFFh F00000h-F0FFFFh to FE0000h-FEFFFFh FF0000h-FF3FFFh FF4000h-FF7FFFh FF8000h-FFBFFFh FFC000h-FFFFFFh
Notes
2 MB
4
32
0
SA002 SA003
Contains four smaller sectors at bottom of addressable memory.
15 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15
128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SA004 to SA018 SA019 to SA034 SA035 to SA050 SA051 to SA066 SA067 to SA082 SA083 to SA098 SA099 to SA114 SA115 to SA130 SA131 to SA146 SA147 to SA162 SA163 to SA178 SA179 to SA194 SA195 to SA210 SA211 to SA226 SA227 to SA242 SA243 to SA257 SA258
All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (see note)
2 MB
4
32
15
SA259 SA260 SA261
Contains four smaller sectors at top of addressable memory.
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005-SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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Table 9.2
Bank Size Sector Count Sector Size (KB)
32 4 32 32 32 7 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 1 MB 8 8 8 8 8 8 8 8 8 8 8 8 8 8 7 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 32 1 MB 4 32 32 32 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0
S29WS128N Sector & Memory Address Map
Sector/ Sector Range
SA000 SA001 SA002 SA003 SA004 to SA010 SA011 to SA018 SA019 to SA026 SA027 to SA034 SA035 to SA042 SA043 to SA050 SA051 to SA058 SA059 to SA066 SA067 to SA074 SA075 to SA082 SA083 to SA090 SA091 to SA098 SA099 to SA106 SA107 to SA114 SA115 to SA122 SA123 to SA129 SA130 SA131 SA132 SA133
Bank
Address Range
000000h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh to 070000h-07FFFFh 080000h-08FFFFh to 0F0000h-0FFFFFh 100000h-10FFFFh to 170000h-17FFFFh 180000h-18FFFFh to 1F0000h-1FFFFFh 200000h-20FFFFh to 270000h-27FFFFh 280000h-28FFFFh to 2F0000h-2FFFFFh 300000h-30FFFFh to 370000h-37FFFFh 380000h-38FFFFh to 3F0000h-3FFFFFh 400000h-40FFFFh to 470000h-47FFFFh 480000h-48FFFFh to 4F0000h-4FFFFFh 500000h-50FFFFh to 570000h-57FFFFh 580000h-58FFFFh to 5F0000h-5FFFFFh 600000h-60FFFFh to 670000h-67FFFFh 680000h-68FFFFh to 6F0000h-6FFFFFh 700000h-70FFFFh to 770000h-77FFFFh 780000h-78FFFFh to 7E0000h-7EFFFFh 7F0000h-7F3FFFh 7F4000h-7F7FFFh 7F8000h-7FBFFFh 7FC000h-7FFFFFh
Notes
1 MB
Contains four smaller sectors at bottom of addressable memory.
All 128 KB sectors. Pattern for sector address range is xx0000h-xxFFFFh. (see note)
Contains four smaller sectors at top of addressable memory.
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed (such as SA005-SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h-xxFFFFh.
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10 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Tables 15.1 and 15.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
10.1
Device Operation Table
The device must be setup appropriately for each operation. Table 10.1 describes the required state of each control pin for any particular operation.
Table 10.1
Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations (Synchronous) Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L L H X L CE# L L L L H X
Device Operations
OE# L L H H X X WE# H H L L X X Addresses Addr In Addr In Addr In Addr In X X DQ15-0 Data Out Data Out I/O I/O HIGH Z HIGH Z RESET# H H H H H L X X X X CLK X X X L L AVD#
X L X X X
H H H H H
Addr In X X X Addr In
X Burst Data Out HIGH Z HIGH Z I/O
H H H L H X H X X
Legend: L = Logic 0, H = Logic 1, X = Don't Care, I/O = Input/Output.
10.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory array, the system must first assert a valid address on Amax- A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. Data is output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#.
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10.3
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system. The device offers both continuous and linear methods of burst read operation, which are discussed in subsections 10.3.4 and 10.3.5, and 10.3.6. Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word (tIACC) of each burst access, the burst mode in which to operate, and when RDY indicates data is ready to be read. Prior to entering the burst mode, the system should first determine the configuration register settings (and read the current register settings if desired via the Read Configuration Register command sequence), and then write the configuration register command sequence. See Section 10.3.7, Configuration Register, and Table 15.1, Memory Array Commands for further details.
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Set Burst Mode Configuration Register Command for Synchronous Mode (CR15 = 0)
Set Burst Mode Configuration Register Command for Asynchronous Mode (CR15 = 1)
Synchronous Read Mode Only
Figure 10.1
Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions: tIACC specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. configuration register setting CR13-CR11: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. The effect is that tIACC is lengthened. The device outputs subsequent words tBACC after the active edge of each successive clock cycle, which also increments the internal address counter. The device outputs burst data at this rate subject to the following operational conditions:
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starting address: whether the address is divisible by four (where A[1:0] is 00). A divisibleby-four address incurs the least number of additional wait states that occur after the initial word. The number of additional wait states required increases for burst operations in which the starting address is one, two, or three locations above the divisible-by-four address (i.e., where A[1:0] is 01, 10, or 11). boundary crossing: There is a boundary at every 128 words due to the internal architecture of the device. One additional wait state must be inserted when crossing this boundary if the memory bus is operating at a high clock frequency. Please refer to the tables below. clock frequency: the speed at which the device is expected to burst data. Higher speeds require additional wait states after the initial word for proper operation. In all cases, with or without latency, the RDY output indicates when the next data is available to be read. Tables 10.2-10.7 reflect wait states required for S29WS256/128N devices. Refer to the "Configuration Register" table (CR11 - CR14) and timing diagrams for more details.
Table 10.2
Word 0 1 2 3 Wait States x ws x ws x ws x ws D0 D1 D2 D3
Address Latency (S29WS256N)
Cycle D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8
Table 10.3
Word 0 1 2 3 Wait States 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws D0 D1 D2 D3
Address Latency (S29WS128N)
Cycle D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8
Table 10.4
Word 0 1 2 3
Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6
Wait States 7 ws 7 ws 7 ws 7 ws
Table 10.5
Word 0 1 2 3
Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 6 ws 6 ws 6 ws 6 ws
Wait States
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Table 10.6
Word 0 1 2 3
Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7 D8 D8 D8 D8
Wait States 5 ws 5 ws 5 ws 5 ws
Table 10.7
Word 0 1 2 3 Wait States 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws 5, 6, 7 ws
Address/Boundary Crossing Latency (S29WS128N)
Cycle D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 1 ws 1 ws D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D4 D4 D5 D5 D5 D5 D6 D6 D6 D6 D7 D7 D7 D7
Note: Setup Configuration Register parameters
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Set Configuration Register Command and Settings: Address 555h, Data D0h Address X00h, Data CR
Command Cycle CR = Configuration Register Bits CR15-CR0
Load Initial Address Address = RA
RA = Read Address
Read Initial Data RD = DQ[15:0]
RD = Read Data
Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing
Refer to the Latency tables.
Read Next Data RD = DQ[15:0] No Delay X Clocks Crossing Boundary? No
Yes
End of Data?
Yes
Completed
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10.3.4
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary (as mentioned above) and the subsequent word line is not being programmed or erased, additional latency cycles are required as reflected by the configuration register table (Table 10.9). If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse.
10.3.5
8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 10.8). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing.
Table 10.8
Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words
Burst Address Groups
Group Address Ranges 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,...
10.3.6
8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8- word mode is 3Ch, the address range to be read would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state.
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10.3.7
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence, before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration Register can also be read using a command sequence (see Table 15.1). The following list describes the register settings.
Table 10.9
CR Bit CR15 CR14 Function Set Device Read Mode Reserved 54 MHz CR13 S29WS128N S29WS256N S29WS128N Programmable Wait State S29WS256N S29WS128N S29WS256N 1 0 0
Configuration Register
Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Read Mode (default) Enabled 1 = S29WS256N at 6 or 7 Wait State setting 0 = All others
66 Mhz 1
80 MHz 1 011 = Data valid on 5th active CLK edge after addresses latched 100 = Data valid on 6th active CLK edge after addresses latched 101 = Data valid on 7th active CLK edge after addresses latched (default) 110 = Reserved 111 = Reserved Inserts wait states before initial data is available. Setting greater number of wait states before initial data reduces latency after initial data. (Notes 1, 2) 0 = RDY signal active low 1 = RDY signal active high (default) 1 = default 0 = RDY active one clock cycle before data 1 = RDY active with data (default) When CR13-CR11 are set to 000, RDY is active with data regardless of CR8 setting. 1 = default 1 = default 0 = default 0 = default 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved)
CR12
1
0
0
CR11
1
CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3
RDY Polarity Reserved RDY Reserved Reserved Reserved Reserved Burst Wrap Around
CR2 CR1 CR0
Burst Length
Notes:
1. 2. 3. Refer to Tables 10.2 - 10.7 for wait states requirements. Refer to Synchronous Burst Read timing diagrams Configuration Register is in the default state upon power-up or hardware reset.
Reading the Configuration Table. The configuration register can be read with a four-cycle command sequence. See Table 15.1 for sequence details. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct state.
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10.4
Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 10.10). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspendread mode if the bank was previously in Erase Suspend). See Table 15.1 for command sequence details.
Table 10.10
Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh
Autoselect Addresses
Read Data
0001h 227Eh 2230 (WS256N) 2231 (WS128N) 2200 DQ15 - DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
Indicator Bits (See Note)
(BA) + 03h
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot Sectors. 01, 10, 11 = Reserved DQ2 = Reserved DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option), 0 = Locked (default) DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed, 0 = Erase disabled
Sector Block Lock/ Unlock
(SA) + 02h
0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 are reserved.
Table 10.11
Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write
Autoselect Entry
Word Address BAx555h BAx2AAh BAx555h Data 0x00AAh 0x0055h 0x0090h
(LLD Function = lld_AutoselectEntryCmd)
Byte Address BAxAAAh BAx555h BAxAAAh
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Table 10.12
Cycle Unlock Cycle 1 Operation Write
Autoselect Exit
Word Address base + XXXh Data 0x00F0h
(LLD Function = lld_AutoselectExitCmd)
Byte Address base + XXXh
Notes: 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
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10.5
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the configuration register (Table 10.8). For any program and or erase operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. Note the following: When the Embedded Program algorithm is complete, the device returns to the read mode. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. A "0" cannot be programmed back to a "1." Attempting to do so causes the device to set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding read shows that the data is still "0." Only erase operations can convert a "0" to a "1." Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries for single word programming operation.
10.5.1
Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this programming operation could be 8-, 16- or 32-bits wide. While this method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 15.1 for the required bus cycles and Figure 10.3 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. During programming, any command (except the Suspend Program command) is ignored. The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.
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A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity.
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Program Command: Address 555h, Data A0h
Setup Command
Program Data to Address: PA, PD
Program Address (PA), Program Data (PD)
Perform Polling Algorithm
(see Write Operation Status flowchart)
Polling Status = Busy? No Yes Polling Status = Done? No
Yes
Error condition (Exceeded Timing Limits)
PASS. Device is in read mode.
FAIL. Issue reset command to return to read array mode.
Figure 10.3
Single Word Program
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Table 10.13
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program
Software Functions and Sample Code
Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */
10.5.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard "word" programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of "word locations minus 1" that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the "Program Buffer to Flash" confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the "write-buffer-page" address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The "write-buffer-page" is selected by using the addresses AMAX - A5. The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple "writebuffer-pages." This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected "writebuffer-page", the operation ABORTs.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the "address/data pair" counter is decremented for every data load operation. Also, the last data loaded at a location before the "Program Buffer to Flash" confirm command is programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-bufferaddress location. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other
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address/data write combinations abort the Write Buffer Programming operation. The device goes "busy." The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer "embedded" programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the "Number of Locations to Program" step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the "Starting Address" during the "write buffer data loading" stage of the operation. Write data other than the "Confirm Command" after the specified number of "data load" cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A "Write-to-Buffer-Abort reset" command sequence is required when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately eight times faster than programming one word at a time.
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Table 10.14
Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count
Software Functions and Sample Code
Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N-1)h
Program Address Program Address
Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h
Notes:
1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. A flash page begins at addresses */ /* evenly divisible by 0x20. */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */
/* Example: Write Buffer Abort Reset */ *( (UINT16 *)addr + 0x555 ) = 0x00AA; *( (UINT16 *)addr + 0x2AA ) = 0x0055; *( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1 /* write unlock cycle 2 /* write buffer abort reset
*/ */ */
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Issue Write Buffer Load Command: Address 555h, Data 25h
Load Word Count to Program Program Data to Address: SA = wc
wc = number of words - 1
Yes wc = 0?
Confirm command: SA = 0x29h
No Wait 4 s (Recommended) Write Buffer Abort Desired? Perform Polling Algorithm Yes Write to a Different Sector Address to Cause Write Buffer Abort
(see Write Operation Status flowchart)
Write Next Word, Decrement wc: PA data , wc = wc - 1
No
Polling Status = Done? No No
Yes
Error?
Yes
Write Buffer Abort? No
Yes
RESET. Issue Write Buffer Abort Reset Command
FAIL. Issue reset command to return to read array mode.
PASS. Device is in read mode.
Figure 10.4 10.5.3 Sector Erase
Write Buffer Programming Operation
The sector erase function erases one or more sectors in the memory array. (See Table 15.1, Memory Array Commands; and Figure 10.5, Sector Erase Operation.) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations.
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After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the DQ3: Sector Erase Timeout State Indicator section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 10.5 illustrates the algorithm for the erase operation. Refer to the Erase and Programming Performance section for parameters and timing diagrams.
Table 10.15
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Sector Erase Command
Software Functions and Sample Code
Operation Write Write Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Sector Address Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address Data 00AAh 0055h 0080h 00AAh 0055h 0030h
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA.
The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)sector_address ) */ )= )= )= )= )= = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0030; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ sector erase command */
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h
Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure
No
Select Additional Sectors? Yes Write Additional Sector Addresses
* Each additional cycle must be written within tSEA timeout * Timeout resets after each additional cycle is written * The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands
No
Poll DQ3. DQ3 = 1? Yes
Yes
Last Sector Selected? No
* No limit on number of sectors * Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data
Wait 4 s (Recommended) Perform Write Operation Status Algorithm (see Figure 10.6)
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Device returns to reading array.
Notes:
1. 2.
FAIL. Write reset command to return to reading array.
See Table 15.1 for erase command sequence. See the section on DQ3 for information on the sector erase timeout.
Figure 10.5
Sector Erase Operation
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10.5.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 15.1. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. The "Command Definition" section in the appendix shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to "Write Operation Status" for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Table 10.16
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command
Software Functions and Sample Code
Operation Write Write Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0080h 00AAh 0055h 0010h
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x000 )
= = = = = =
0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0010;
/* /* /* /* /* /*
write write write write write write
unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ chip erase command */
10.5.5
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written after the tSEA time-out period has expired and during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. Additionaly, when an Erase Suspend command is written during an active erase operation, status information is unavailable during the transition from the sector erase operation to the erase suspended state.
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After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erasesuspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 10.20 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspendread mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to the "Write Buffer Programming Operation" section and the "Autoselect Command Sequence" section for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Table 10.17
Cycle 1 Operation Write
Software Functions and Sample Code
Byte Address Bank Address Word Address Bank Address Data 00B0h
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */
Cycle 1
Operation Write
Byte Address Bank Address
Word Address Bank Address
Data 0030h
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command /* The flash needs adequate time in the resume state */ */
10.5.6
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a "Write to Buffer" programming operation so that data can read from any nonsuspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. Addresses are "don't-cares" when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region.
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The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system must write the Program Resume command (address bits are "don't care") to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.
Table 10.18
Cycle 1 Operation Write
Software Functions and Sample Code
Byte Address Bank Address Word Address Bank Address Data 00B0h
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */
Cycle 1
Operation Write
Byte Address Bank Address
Word Address Bank Address
Data 0030h
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */
10.5.7
Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the ACC function. This method is faster than the standard chip program and erase command sequences. The accelerated chip program and erase functions must not be used more than 10 times per sector. In addition, accelerated chip program and erase should be performed at room temperature (25C 10C). If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a "Write-to-Buffer-Abort Reset" is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Sectors must be unlocked prior to raising ACC to VHH. The ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage may result.
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The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. ACC locks all sector if set to VIL; ACC should be set to VIH for all other conditions.
10.5.8
Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four cycles. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The "Command Definition Summary" section shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low Level Driver User's Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
Table 10.19
Cycle 1 2 3 Description Unlock Unlock Entry Command
Software Functions and Sample Code
Operation Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0020h
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/* Example: Unlock Bypass Entry Command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock *( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock /* At this point, programming only takes two write cycles. /* Once you enter Unlock Bypass Mode, do a series of like /* operations (programming or sector erase) and then exit /* Unlock Bypass Mode before beginning a different type of /* operations.
cycle 1 cycle 2 bypass command */ */ */ */ */
*/ */ */
Cycle 1 2
Description Program Setup Command Program Command
Operation Write Write
Byte Address Base + xxxh Program Address
Word Address Base +xxxh Program Address
Data 00A0h Program Data
/* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; *( (UINT16 *)pa ) = data; /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */
/* write program setup command /* write data to be programmed
*/ */
Cycle 1 2
Description Reset Cycle 1 Reset Cycle 2
Operation Write Write
Byte Address Base + xxxh Base + xxxh
Word Address Base +xxxh Base +xxxh
Data 0090h 0000h
/* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000;
10.5.9
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the writebuffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.
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Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read cycles. See the following for more information: Table 10.20, Write Operation Status, shows the outputs for Data# Polling on DQ7. Figure 10.6, Write Operation Status Flowchart, shows the Data# Polling algorithm; and Figure 14.17, Data# Polling Timings (During Embedded Algorithm), shows the Data# Polling timing diagram.
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START
Read 1
(Note 6) DQ7=valid data? NO
YES
Erase Operation Complete
Read 1 DQ5=1? NO
YES
Read 2
YES Read3= valid data? NO
YES
Write Buffer Programming?
Read 2
Read 3 Program Operation Failed YES
Programming Operation?
NO Read 3 Device BUSY, Re-Poll
NO (Note 3) (Note 1) DQ6 toggling? YES TIMEOUT (Note 1) DQ6 toggling? NO (Note 2) Device BUSY, Re-Poll Read 2 DQ2 toggling? NO YES DEVICE ERROR (Note 5)
(Note 4) Read3 DQ1=1?
YES
NO
NO
YES
Device BUSY, Re-Poll Erase Operation Complete Device in Erase/Suspend Mode
Read 3
Read3 DQ1=1 AND DQ7 Valid Data?
YES
Write Buffer Operation Failed
NO Notes: 1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3) May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4) Write buffer error if DQ1 of last read =1. 5) Invalid state, use RESET command to exit operation. 6) Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) Data polling algorithm valid for all operations except advanced sector protection.
Device BUSY, Re-Poll
Figure 10.6
Write Operation Status Flowchart
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DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See the following for additional information: Figure 10.6, Write Operation Status Flowchart; Figure 14.18, Toggle Bit Timings (During Embedded Algorithm), and Table 10.20. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.
DQ2: Toggle Bit II. The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a par-
ticular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14.10 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 10.6, the "DQ6: Toggle Bit I" section, and Figures 14.17-14.20.
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it
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may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 10.6 for more details. Note: When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and DQ2 toggle between high and low states in a series of consecutive and con-tiguous status read cycles. In order for this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. If it is not possible to temporarily prevent reads to other memory banks, then it is recommended to use the DQ7 status bit as the alternative method of determining the active or inactive status of the write operation.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1."Under both these conditions, the system must write the reset command to return to the read mode (or to the erasesuspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10.20 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details.
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Table 10.20
Program Suspend Mode (Note 3) Reading within Program Suspended Sector Reading within Non-Program Suspended Sector BUSY State Exceeded Timing Limits ABORT State
Write Operation Status
INVALID (Not Allowed) Data DQ7# DQ7# DQ7# INVALID (Not Allowed) Data Toggle Toggle Toggle INVALID (Not Allowed) Data 0 1 0 INVALID (Not Allowed) Data N/A N/A N/A INVALID (Not Allowed) Data N/A N/A N/A INVALID (Not Allowed) Data 0 0 1
Write to Buffer (Note 5)
Notes:
1. 2. 3. 4. 5. 6. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details. Data are invalid for addresses in a Program Suspended sector. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. For any address changes after CE# assertion, re-assertion of CE# might be required after the addresses become stable for data polling during the erase suspend operation using DQ2/DQ6.
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10.6
Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 14.24, Back-to-Back Read/Write Cycle Timings, shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics (CMOS Compatible) table for read-while-program and read-while-erase current specification.
10.7
Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 9.1-9.2 indicate the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A "bank address" is the set of address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. ICC2 in "DC Characteristics" represents the active current specification for the write mode. "AC Characteristics-Synchronous" and "AC Characteristics-Asynchronous" contain timing specification tables and timing diagrams for write operations.
10.8
Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#. When the device is configured to operate in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the RDY pin (depending on the setting for bit 10 in the Configuration Register). It is recommended that the host system set CR13-CR11 in the Configuration Register to the appropriate number of wait states to ensure optimal burst mode operation (see Table 10.9, Configuration Register). Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same time that data is ready, or one cycle before data is ready.
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10.9
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. See Figures 14.5 and 14.12 for timing diagrams.
10.10 Software Reset
Software reset is part of the command set (see Table 15.1) that also returns the device to array read mode and must be used for the following conditions: 1. 2. 3. 4. 5. to exit Autoselect mode when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed exit sector lock/unlock operation. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode. after any aborted operations
Table 10.21
Cycle Reset Command
Reset LLD Function = lld_ResetCmd)
Operation Write Byte Address Base + xxxh Word Address Base + xxxh Data 00F0h
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command: This command resets the banks to the read and address bits are ignored. Reset commands are ignored once erasure has begun until the operation is complete. Once programming begins, the device ignores reset commands until the operation is complete The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command may be also written during an Autoselect command sequence. If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.
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If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see the command table for details].
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11
Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 11.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = VIL (All sectors locked)
Password Method
(DQ2)
Persistent Method
(DQ1)
(All boot sectors locked)
WP# = VIL
64-bit Password
(One Time Protect)
PPB Lock Bit1,2,3 0 = PPBs Locked 1 = PPBs Unlocked
1. Bit is volatile, and defaults to "1" on reset. 2. Programming to "0" locks all PPBs to their current state. 3. Once programmed to "0", requires hardware reset to unlock.
Memory Array
Sector 0 Sector 1 Sector 2
Persistent Protection Bit (PPB)4,5
PPB 0 PPB 1 PPB 2
Dynamic Protection Bit (DYB)6,7,8
DYB 0 DYB 1 DYB 2
Sector N-2 Sector N-1 Sector N
3
PPB N-2 PPB N-1 PPB N
4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively
DYB N-2 DYB N-1 DYB N
6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is "1" (unprotected). 8. Volatile Bits: defaults to user choice upon power-up (see ordering options).
3. N = Highest Address Sector.
Figure 11.1
Advanced Sector Protection/Unprotection
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11.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option. The device programmer or host system must then choose which sector protection method to use. Programming (setting to "0") any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: Lock Register Persistent Protection Mode Lock Bit (DQ1) Lock Register Password Protection Mode Lock Bit (DQ2)
Table 11.1
Device
S29WS256N
Lock Register
DQ3
1
DQ15-05
1
DQ4
1 DYB Lock Boot Bit 0 = sectors power up protected 1 = sectors power up unprotected
DQ2
Password Protection Mode Lock Bit
DQ1
Persistent Protection Mode Lock Bit
DQ0
Customer SecSi Sector Protection Bit
PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled
S29WS128N
Undefined
Password Protection Mode Lock Bit
Persistent Protection Mode Lock Bit
SecSi Sector Protection Bit
For programming lock register bits refer to Table 15.2. Notes 1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. After selecting a sector protection method, each sector can operate in any of the following three states: 1. 2. 3. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. Dynamically locked. The selected sectors are protected and can be altered via software commands. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 11.2-.
11.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring.
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Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Each PPB is individually programmed and all are erased in parallel. While programming PPB for a sector, array data can be read from any other bank, except Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed. Entry command disables reads and writes for the bank selected. Reads within that bank return the PPB status for that sector. Reads from other banks are allowed while writes are not allowed. All Reads must be performed using the Asynchronous mode. The specific sector address (A23-A14 WS256N, A22-A14 WS128N) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and timesout without programming or erasing the PPB. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation.
10. Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 11. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 11.2.
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Enter PPB Command Set. Addr = BA
Program PPB Bit. Addr = SA
Read Byte Twice Addr = SA0
DQ6 = Toggle? Yes No
No
DQ5 = 1? Yes Read Byte Twice Addr = SA0 Wait 500 s
DQ6 = Toggle? Yes
No
Read Byte. Addr = SA
No
DQ0 = '1' (Erase) '0' (Pgm.)? Yes
FAIL
Issue Reset Command
PASS
Exit PPB Command Set
Figure 11.2
PPB Program/Erase Algorithm
11.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to "1"). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed.
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Notes 1. The DYBs can be set (programmed to "0") or cleared (erased to "1") as often as needed. When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. 2. 3. 4. 5. If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectors may be modified depending upon the PPB state of that sector (see Table 11.2). The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to "0"). It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.
6.
11.4
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to "0"), it locks all PPBs and when cleared (programmed to "1"), allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. 2. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. The PPB Lock Bit must be set (programmed to "0") only after all PPBs are configured to the desired settings.
11.5
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set "0" to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
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Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out with the cell as a "0". The password is all "1"s when shipped from the factory. All 64-bit password combinations are valid as a password. There is no means to verify what the password is after it is set. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. The Password Mode Lock Bit is not erasable. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. The exact password must be entered in order for the unlocking function to occur.
2. 3. 4. 5. 6. 7. 8. 9.
10. The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. Password verification is only allowed during the password programming operation. 13. All further commands to the password region are disabled and all operations are ignored. 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Enter Lock Register Command: Address 555h, Data 40h
Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD
XXXh = Address don't care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once.
Wait 4 s (Recommended)
Perform Polling Algorithm
(see Write Operation Status flowchart)
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array.
FAIL. Write rest command to return to reading array.
Figure 11.3
Lock Register Program Algorithm
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Table 11.2
Advanced Sector Protection Software Examples
Sector PPB 0 = protected 1 = unprotected
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
Unique Device PPB Lock Bit 0 = locked 1 = unlocked
Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector
Sector DYB 0 = protected 1 = unprotected
x x 1 0 x x 0 1
Sector Protection Status
Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected
Figure 11.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to "0"), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to "1") through a hardware reset or power cycle. See also Figure 11.1 for an overview of the Advanced Sector Protection feature.
11.6
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control: When WP# is at VIL, the four outermost sectors are locked (device specific). When ACC is at VIL, all sectors are locked. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
11.6.1
WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the "outermost" boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution
11.6.2
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are disabled and hence all sectors are protected.
11.6.3
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
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The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
11.6.4 11.6.5
Write Pulse "Glitch Protection"
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
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12 Power Conservation Modes
12.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in "DC Characteristics" represents the standby current specification
12.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in DC Characteristics (CMOS Compatible) represents the automatic sleep mode current specification.
12.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
12.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
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13 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. Please note the following general conditions: While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads can be performed in the Asynchronous or Synchronous mode. Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h. Reads outside of sector 0 return memory array data. Continuous burst read past the maximum address is undefined. Sector 0 is remapped from memory array to Secured Silicon Sector array. Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.
Table 13.1
Sector Customer Factory Sector Size 128 words 128 words
Addresses
Address Range 000080h-0000FFh 000000h-00007Fh
13.1
Factory Secured SiliconSector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a "1". This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: A random, 8 Word secure ESN only within the Factory Secured Silicon Sector Customer code within the Customer Secured Silicon Sector through the SpansionTM programming service. Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services.
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13.2
Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to "0"), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to "1." The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is available. Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0.
13.3
Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See Command Definition Table [Secured Silicon Sector Command Table, Appendix Table 15.1 for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read customer and factory Secured Silicon areas Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User's Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
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Table 13.2
Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle
Secured Silicon Sector Entry
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0088h
(LLD Function = lld_SecSiSectorEntryCmd)
Operation Write Write Write
Note: Base = Base Address.
/* Example: SecSi Sector *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr
Entry Command */ + 0x555 ) = 0x00AA; + 0x2AA ) = 0x0055; + 0x555 ) = 0x0088;
/* write unlock cycle 1 /* write unlock cycle 2 /* write Secsi Sector Entry Cmd
*/ */ */
Table 13.3
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program
Secured Silicon Sector Program
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
(LLD Function = lld_ProgramCmd)
Operation Write Write Write Write
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */ /* words using the programming algorithm. */
Table 13.4
Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle
Secured Silicon Sector Exit
Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0090h
(LLD Function = lld_SecSiSectorExitCmd)
Operation Write Write Write
Note: Base = Base Address.
/* Example: SecSi Sector *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr *( (UINT16 *)base_addr Exit Command */ + 0x555 ) = 0x00AA; + 0x2AA ) = 0x0055; + 0x555 ) = 0x0090; + 0x000 ) = 0x0000; /* /* /* /* write write write write unlock cycle unlock cycle SecSi Sector SecSi Sector 1 2 Exit cycle 3 Exit cycle 4 */ */ */ */
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14 Electrical Specifications
14.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +2.5 V ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +9.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 14.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 14.2. 2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 14.1. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
3. 4.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
VCC +2.0 V VCC +0.5 V 1.0 V 20 ns
20 ns
20 ns
Figure 14.1 Maximum Negative Overshoot Waveform
Figure 14.2 Maximum Positive Overshoot Waveform
Note:The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
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14.2
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 V to +1.95 V Notes: Operating ranges define those limits between which the functionality of the device is guaranteed.
14.3
Test Conditions
Device Under Test CL
Figure 14.3 Table 14.1
Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Setup
Test Specifications
All Speed Options 30 3.0 @ 54, 66 MHz 2.5 @ 80 MHz 0.0-VCC VCC/2 VCC/2 Unit pF ns V V V
Note: The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
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14.4
Key to Switching Waveforms
Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs
Notes:
1. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
14.5
Switching Waveforms
All Inputs and Outputs VCC 0.0 V Input VCC/2 Measurement Level VCC/2 Output
Figure 14.4
Input Waveforms and Measurement Levels
14.6
VCC Power-up
Parameter tVCS
Notes:
1. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
Description VCC Setup Time
Test Setup Min
Speed 1
Unit ms
2.
S29WS128N: VCC ramp rate is > 1V/ 100 s and for VCC ramp rate of < 1 V / 100 s a hardware reset is required.
tVCS VCC
RESET#
Figure 14.5
VCC Power-up Diagram
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14.7
DC Characteristics (CMOS Compatible)
Parameter ILI ILO Description (Notes) Input Load Current Output Leakage Current (2) Test Conditions (Notes 1, 8) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length =8 CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous 54 MHz 66 MHz 80 MHz 54 MHz 66 MHz 80 MHz 54 MHz 66 MHz 80 MHz 54 MHz 66 MHz 80 MHz 10 MHz CE# = VIL, OE# = VIH, WE# = VIH CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH, ACC = VIH @ 5 MHz CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 9.5 V VCC = 1.8 V VCC = 1.8 V IOL = 100 A, VCC = VCC min = VCC IOH = -100 A, VCC = VCC min = VCC VCC 8.5 9.5 1.4 VACC VCC -0.5 VCC - 0.4 5 MHz 1 MHz VACC VCC VACC VCC 27 28 30 28 30 32 29 32 34 32 35 38 34 17 4 1 24 1 20 70 50 2 6 14 Min Typ Max 1 1 54 60 66 48 54 60 42 48 54 36 42 48 45 26 7 5 52.5 5 70 250 60 70 20 20 0.4 VCC + 0.4 0.1 Unit A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A mA A A A mA A mA mA V V V V V V
ICC1
VCC Active Asynchronous Read Current (3)
ICC2 ICC3 ICC4 ICC5 ICC6 IACC VIL VIH VOL VOH VHH VLKO
VCC Active Write Current (4) VCC Standby Current (5, 6) VCC Reset Current (6) VCC Active Current (Read While Write) (6) VCC Sleep Current (6) Accelerated Program Current (7) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax. 2. CE# must be set high when measuring the RDY pin. 3. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 6. VIH = VCC 0.2 V and VIL > -0.1 V. 7. Total current during accelerated programming is the sum of VACC and VCC currents. 8. VACC = VHH on ACC input. 9. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
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14.8
AC Characteristics
CLK Characterization
Parameter fCLK tCLK tCH tCL tCR tCF Description CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Max Min Min 54 MHz 54 18.5 7.4 66 MHz 66 15.1 6.1 80 MHz 80 12.5 5.0 Unit MHz ns ns
14.8.1
Max
3
3
2.5
ns
Notes: 1. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
2.
Not 100% tested.
tCLK tCH tCL
CLK
tCR
tCF
Figure 14.6
CLK Characterization
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14.8.2
Synchronous/Burst Read
Parameter JEDEC Standard tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tCAS tAVC tAVD fCLK Latency Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z (Note 2) Output Enable to High Z (Note 2) CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse Minimum clock frequency Description Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Min
1
54 MHz
66 MHz 80
80 MHz
Unit ns
13.5 5 7 4 13.5 13.5
11.2 4 6 3 11.2 11.2 10 10 4
9
ns ns ns ns
9
ns ns ns ns ns
5 13.5
4 11.2 0 4 8
1
3.5 9
ns ns ns ns ns
1
MHz
Notes:
1. Addresses are latched on the first rising edge of CLK. 2. Not 100% tested. 3. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
Table 14.2
Max Frequency 01 MHz < Freq. 14 MHz 14 MHz < Freq. 27 MHz 27 MHz < Freq. 40 MHz 40 MHz < Freq. 54 MHz 54 MHz < Freq. 67 MHz 67 MHz < Freq. 80 MHz
Synchronous Wait State Requirements
Wait State Requirement 2 3 4 5 6 7
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14.8.3
Timing Diagrams
5 cycles for initial access shown.
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Aa
18.5 ns typ. (54 MHz)
tCEZ 6 7
2
3
4
5
tAVD
tACH Data (n) tIACC OE# tOE RDY (n)
Hi-Z Da Da + 1
tBACC
Hi-Z Da + 2 Da + 3 Da + n
tBDH tRACC
tOEZ
Hi-Z
tCR
tRDYS
Hi-Z Da Da + 1 Da + 2 Da + 2 Da + n
Data (n + 1)
RDY (n + 1)
Hi-Z
Hi-Z
Data (n + 2)
Da Da + 1 Da + 1 Da + 1 Da + n
Hi-Z
RDY (n + 2)
Hi-Z
Hi-Z
Data (n + 3)
Da Da Da Da Da + n
Hi-Z
RDY (n + 3)
Hi-Z
Hi-Z
Notes: 1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. 3. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode.
Figure 14.7
CLK Synchronous Burst Mode Read
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tCES CE# 1 CLK tAVC AVD# tACS Addresses
Ac
7 cycles for initial access shown.
2
3
4
5
6
7
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D8
DB
tBDH tRACC
tOE
tRACC
tRDYS
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. The device is in synchronous mode with wrap around. D8-DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (0-F).
Figure 14.8
tCES CE# 1 CLK tAVC AVD# tACS Addresses
Ac 7 cycles for initial access shown.
8-word Linear Burst with Wrap Around
2
3
4
5
6
7
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z DC DD
tBACC
DE
DF
D8
DB
tBDH
tOE
tRACC
tRACC
tRDYS
Notes:
1. 2. 3. 4. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. The device is in asynchronous mode with out wrap around. DC-D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 1st address in range (c-13).
Figure 14.9
8-word Linear Burst without Wrap Around
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tCES CE# ~ ~ ~ ~ 1 CLK tAVC AVD# tACS Addresses
Aa
6 wait cycles for initial access shown.
tCEZ 7
~ ~
5 ~ ~
6
tAVD
tACH Data tIACC OE# tCR RDY
Hi-Z Da Da+1
tBACC
Hi-Z Da+2 Da+3 Da + n
tBDH tRACC tOE
tOEZ
Hi-Z
tRDYS
Notes:
1. 2. Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data.
Figure 14.10 14.8.4
Linear Burst with RDY Set One Cycle Before Data
AC Characteristics--Asynchronous Read
Parameter JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Description Access Time from CE# Low Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Output Enable Hold Time Read Data# Polling Max Max Min Min Min Max Min Min Max Min 7 13.5 0 10 10 0 54 MHz 66 MHz 80 80 8 4 6
80 MHz
Unit ns ns ns ns ns ns ns ns ns ns
Output Enable to High Z (see Note) CE# Setup Time to AVD#
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS128N.
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CE# tOE tOEH WE# Data tACC Addresses tCAS AVD# tAVDP tAAVDS
Note: RA = Read Address, RD = Read Data.
OE#
tCE Valid RD
tOEZ
RA tAAVDH
Figure 14.11
Asynchronous Mode Read
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14.8.5
Hardware Reset (RESET#)
Parameter JEDEC Std. tRP tRH RESET# Pulse Width Reset High Time Before Read (See Note) Description Min Min All Speed Options 30 200 Unit s ns
Notes:
1. Not 100% tested.
2. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
CE#, OE# tRH RESET# tRP
Figure 14.12
Reset Timings
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14.8.6
Parameter JEDEC
tAVAV tAVWL tWLAX
Erase/Program Timing
Description
Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Setup Time to CLK AVD# Hold Time to CLK Clock Setup Time to WE# Noise Pulse Margin on WE# Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Erase within a Protected Sector Toggle Time During Programming Within a Protected Sector Synchronous Asynchronous Synchronous Asynchronous Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Max Max Max Typ Typ 45 0 0 0 0 30 20 0 500 1 5 5 5 5 5 5 3 50 20 20 0 0
Standard
tWC tAS tAH tAVDP
54 MHz
66 MHz
80 5 0 9 20 8 20
80 MHz
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns s s s s s
tDVWH tWHDX tGHWL tWHEH tWLWH tWHWL
tDS tDH tGHWL tCAS tCH tWP tWPH tSR/W tVID tVIDS
tELWL
tCS tAVSW tAVHW tAVSC tAVHC tCSW tWEP tSEA tESL tPSL tASP tPSP
Notes:
1. 2. 3. 4. 5. 6. Not 100% tested. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the rising edge of CLK. See the Erase and Programming Performance section for more information. Does not include the preprogramming time. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
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VIH
Erase Command Sequence (last two cycles)
Read Status Data
CLK
VIL
tAVDP AVD# tAS Addresses 2AAh tAH SA
555h for chip erase 10h for chip erase
VA
In Progress
VA
Data
55h
30h tDS tDH
Complete
CE#
OE# tWP WE# tCS tVCS VCC
tCH
tWHWH2 tWPH tWC
Figure 14.13
Chip/Sector Erase Operation Timings
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Program Command Sequence (last two cycles)
Read Status Data
VIH
CLK
VIL
tAVSW tAVDP tAVHW
AVD# tAS tAH Addresses 555h PA VA
In Progress
VA
Data tCAS CE#
A0h tDS tDH
PD
Complete
OE# tWP WE#
tCH
tWHWH1 tCS tWC tVCS VCC tWPH
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A23-A14 for the WS256N (A22-A14 for the WS128N) are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 14.14
Program Operation Timing Using AVD#
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Program Command Sequence (last two cycles) tAVCH CLK tAS tAH tAVSC AVD# tAVDP Addresses 555h PA VA
Read Status Data
VA
In Progress
Data tCAS CE#
A0h
PD tDS tDH
Complete
OE#
tCSW tWP
tCH
WE# tWHWH1 tWPH tWC
tVCS VCC
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A23-A14 for the WS256N (A22-A14 for the WS128N) are don't care during command sequence unlock cycles. 4. Addresses are latched on the first rising edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 14.15
Program Operation Timing Using CLK in Relationship to AVD#
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CE#
AVD# WE# Addresses Data Don't Care A0h
PA Don't Care PD Don't Care
OE# ACC
VID
tVIDS tVID
VIL or VIH
Note: Use setup and hold times from conventional program operation.
Figure 14.16
Accelerated Unlock Bypass Programming Timing
AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA
High Z
tCEZ
tOE
tOEZ
High Z
Data
Status Data
Status Data
Notes:
1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is completeData# Polling outputs true data.
Figure 14.17
Data# Polling Timings (During Embedded Algorithm)
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AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA
High Z
tCEZ
tOE
tOEZ
Data
High Z
Status Data
Status Data
Notes:
1. 2. Status reads in figure are shown as asynchronous. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
Figure 14.18
Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC tIACC Status Data Status Data
Data
RDY
Notes:
1. 2. 3. The timings are similar to synchronous read timings. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, . RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before data.
Figure 14.19
Synchronous Data Polling Timings/Toggle Bit Timings
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Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 14.20
DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124 CLK Address (hex) AVD# 7C (stays high)
C125 7D
C126 7E
C127 7F
C127 7F
C128 80
C129 81
C130 82
C131 83
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D124
D125
D126
D127
D128
D129
D130
OE#, CE#
(stays low)
Notes:
1. 2. 3. 4. 5. RDY(1) active with data (D8 = 1 in the Configuration Register). RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing a bank in the process of performing an erase or program. RDY does not go low and no additional wait states are required for WS 5.
Figure 14.21
Latency with Boundary Crossing when Frequency > 66 MHz
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Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124 CLK Address (hex) AVD# 7C (stays high)
C125 7D
C126 7E
C127 7F
C127 7F
tRACC RDY(1) tRACC RDY(2)
latency latency
tRACC
tRACC
Data
D124
D125
D126
D127
Read Status
OE#, CE#
Notes:
1. 2. 3. 4. 5.
(stays low)
RDY(1) active with data (D8 = 1 in the Configuration Register). RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. RDY does not go low and no additional wait states are required for WS 5.
Figure 14.22
Latency with Boundary Crossing into Program/Erase Bank
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Data
D0
D1
AVD#
Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following addresses being latched
OE# 1 CLK 0 1 2 3
4
5
6
7
2
3
4
5
number of clock cycles programmed
Wait State Configuration Register Setup: D13, D13, D13, D13, D13, D12, D12, D12, D12, D12, D11 D11 D11 D11 D11 = = = = = "111" "110" "101" "100" "011" Reserved Reserved 5 programmed, 7 total 4 programmed, 6 total 3 programmed, 5 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to "101".
Figure 14.23
Example of Wait States Insertion
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Last Cycle in Program or Sector Erase Command Sequence
Read status (at least two cycles) in same bank and/or array data from other bank
Begin another write or program command sequence
tWrite Cycle
tRead Cycle
tRead Cycle
tWrite Cycle
CE#
OE# tOE tOEH WE# tWPH tWP tDS
PD/30h
tGHWL
tACC tDH
RD
tOEZ tOEH
RD AAh
Data
tSR/W Addresses
PA/SA RA RA 555h
tAS AVD# tAH Note: Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information.
Figure 14.24 Back-to-Back Read/Write Cycle Timings
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14.8.7
Erase and Programming Performance
Parameter Sector Erase Time 64 Kword 16 Kword VCC VCC VCC Chip Erase Time ACC Single Word Programming Time (Note 8) Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time VCC ACC VCC ACC VCC ACC VCC Chip Programming Time (Note 3) ACC Typ (Note 1) 0.6 <0.15 153.6 (WS256N) 77.4 (WS128N) 130.6 (WS256N) 65.8 (WS128N) 40 24 9.4 6 300 192 157.3 (WS256N) 78.6 (WS128N) 100.7 (WS256N) 50.3 (WS128N) Max (Note 2) 3.5 2 308 (WS256N) 154 (WS128N) 262 (WS256N) 132 (WS128N) 400 240 94 60 3000 1920 314.6 (WS256N) 157.3 (WS128N) 201.3 (WS256N) 100.7 (WS128N) Unit s Excludes 00h programming prior to erasure (Note 4) Comments
s
s
s
s
s
Excludes system level overhead (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 1.70 V, 100,000 cycles. 3. Typical chip programming time is considerably less than the maximum chip programming time listed, and is based on utilizing the Write Buffer. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See the Appendix for further information on command definitions. 6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. 7. Refer to Application Note "Erase Suspend/Resume Timing" for more details. 8. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 9. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
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14.8.8
BGA Ball Capacitance
Parameter Symbol CIN COUT CIN2
Notes:
1. Sampled, not 100% tested. 2. Test conditions TA = 25C; f = 1.0 MHz. 3. The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance
Test Setup VIN = 0 VOUT = 0 VIN = 0
Typ. 5.3 5.8 6.3
Max 6.3 6.8 7.3
Unit pF pF pF
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15 Appendix
This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see the Additional Resources section on page 23, or explore the Web at www.amd.com and www.fujitsu.com.
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Table 15.1
Cycles Command Sequence (Notes) Asynchronous Read (6) Reset (7) Manufacturer ID Device ID (9) Indicator Bits (10) First Addr Data RA RD XXX F0 555 AA 555 AA 555 555 555 SA 555 555 555 BA BA 555 555 [BA]555 555 XXX XXX XXX 555 555 00 555 AA AA AA 29 AA AA AA B0 30 AA AA 98 AA A0 98 90 AA AA Data AA
Memory Array Commands
Second Addr Data Bus Cycles (Notes 1-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data
Autoselect (8)
1 1 4 6 4 4 6 1 3 6 6 1 1 4 4 1 3 2 1 2 3 4 1 4
2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA
55 55 55 55 55 55 55 55
[BA]555 [BA]555 [BA]555 555 PA 555 555 555
90 90 90 A0 25 F0 80 80
[BA]X00 [BA]X01 [BA]X03 PA PA
0001 227E Data PD WC
BA+X0E
Data
BA+X0F
2200
Unlock Bypass Mode
Program Write to Buffer (11) Program Buffer to Flash Write to Buffer Abort Reset (12) Chip Erase Sector Erase Erase/Program Suspend (13) Erase/Program Resume (14) Set Configuration Register (18) Read Configuration Register CFI Query (15) Entry Program (16) CFI (16) Reset Entry Program (17) Read (17) Exit (17)
PA
PD
WBL
PD
555 555
AA AA
2AA 2AA
55 55
555 SA
10 30
2AA 2AA 2AA PA XXX 2AA 2AA
55 55 55 PD 00 55 55
555 555 555
D0 C6 20
X00 X00
CR CR
Secured Silicon Sector
555 555
88 A0
PA
PD
2AA
55
555
90
XXX
00
Legend: X = Don't care. RA = Read Address. RD = Read Data. PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. Notes: 1. See Table 10.1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. 4. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 6. No unlock or command cycles required when bank is reading array data. 7. Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The system must provide the bank address. See Autoselect section for more information. 9. Data in cycle 5 is 2230 (WS256N) or 2231 (WS128N). 10. See Table 10.9 for indicator bit values. 11. Total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. Command sequence resets device for next command after writeto-buffer operation.
SA = Sector Address. WS256N = A23-A14; WS128N = A22-A14. BA = Bank Address. WS256N = A23-A20; WS128N = A22-A20. CR = Configuration Register data bits D15-D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.
13. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Address equals 55h on all future devices, but 555h for WS256N/128N. 16. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data. 17. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. Requires reset command to configure the Configuration Register.
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Table 15.2
Cycles Command Sequence (Notes) Command Set Entry (5) Lock Program (6, 12) Register Read (6) Bits Command Set Exit (7) Command Set Entry (5) Program [0-3] (8) Password Read (9) Protection Unlock Command Set Exit (7) Command Set Entry (5) PPB Program (10) Non-Volatile Sector All PPB Erase (10, 11) Protection (PPB) PPB Status Read Command Set Exit (7) Global Command Set Entry (5) Volatile Sector PPB Lock Bit Set Protection PPB Lock Bit Status Read Freeze Command Set Exit (7) (PPB Lock) Volatile Sector Protection (DYB) Command Set Entry (5) DYB Set DYB Clear DYB Status Read Command Set Exit (7) First Addr Data 555 AA XX A0 77 data XX 90 555 AA XX A0 0...00 PWD0 00 25 XX 90 555 AA XX A0 XX 80 SA RD(0) XX 90 555 AA XX A0 BA RD(0) XX 555 XX XX SA XX 90 AA A0 A0 RD(0) 90
Sector Protection Commands
Second Addr Data 2AA 55 77/00 data Bus Cycles (Notes 1-4) Third Fourth Fifth Addr Data Addr Data Addr Data 555 40 Sixth Addr Data Seventh Addr Data
3 2 1 2 3 2 4 7 2 3 2 2 1 2 3 2 1 2 3 2 2 1 2
XX 00 2AA 55 555 60 00 PWD[0-3] 0...01 PWD1 0...02 PWD2 00 03 00 PWD0 XX 00 2AA 55 [BA]555 C0 SA 00 00 30 XX 2AA XX XX 2AA SA SA XX 00 55 00 00 55 00 01 00 [BA]555 E0
0...03 PWD3 01 PWD1
02
PWD2
03
PWD3
00
29
[BA]555
50
Legend: X = Don't care. RA = Address of the memory location to be read. PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to `0' for protection while PD(2), bit[2] must be left as `1'. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to `0' for protection while PD(1), bit[1] must be left as `1'. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Sector Address. WS256N = A23-A14; WS128N = A22-A14. Notes: 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the WS256N only. See Tables 11.1 and 11.2 for explanation of lock bits. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state.
BA = Bank Address. WS256N = A23-A20; WS128N = A22-A20. PWD3-PWD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1, DQ2 = 1. 8. Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is required for reading password. 10. See Figure 11.2 for details. 11. "All PPB Erase" command pre-programs all PPBs before erasure to prevent over-erasure. 12. The second cycle address for the lock register program operation is 77 for S29WS256N; however, for WS128N this address is 00.
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15.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 15.3-15.6) within that bank. All reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: CFI Entry command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* Example: CFI Exit command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write CFI entry command */
/* write cfi exit command
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.
Table 15.3
Addresses
10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah
CFI Query Identification String
Description
Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Data
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Table 15.4
Addresses
1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
System Interface String
Description
Data
0017h 0019h 0000h 0000h 0006h 0009h 000Ah 0000h 0004h 0004h 0003h 0000h VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt
VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 15.5
Addresses
27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch
Device Geometry Definition
Description
Data
0019h (WS256N) 0018h (WS128N) 0001h 0000h 0006h 0000h 0003h 0003h 0000h 0080h 0000h 00FDh (WS256N) 007Dh (WS128N) 0000h 0000h 0002h 0003h 0000h 0080h 0000h 0000h 0000h 0000h 0000h
Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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Table 15.6
Addresses
40h 41h 42h 43h 44h
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0100 = 0.11 m Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08 = Advanced Sector Protection Simultaneous Operation Number of Sectors in all banks except boot bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 0001h = Dual Boot Device Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01=Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns Erase Suspend Time-out Maximum 2N ns Program Suspend Time-out Maximum 2N ns Bank Organization: X = Number of banks Bank 0 Region Information. X = Number of sectors in bank Bank 1 Region Information. X = Number of sectors in bank
Data
0050h 0052h 0049h 0031h 0034h
45h
0100h
46h
0002h
47h
0001h
48h
0000h
49h
0008h 00F3h (WS256N) 007Bh (WS128N) 0001h
4Ah
4Bh
4Ch
0000h
4Dh
0085h
4Eh
0095h
4Fh 50h 51h 52h 53h
0001h 0001h 0001h 0007h 0014h
54h 55h 56h 57h 58h 59h
0014h 0005h 0005h 0010h 0013h (WS256N) 000Bh (WS128N) 0010h (WS256N) 0008h (WS128N)
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Table 15.6
Addresses
5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h
Primary Vendor-Specific Extended Query (Continued)
Data Description Bank 2 Region Information. X = Number of sectors in bank Bank 3 Region Information. X = Number of sectors in bank Bank 4 Region Information. X = Number of sectors in bank Bank 5 Region Information. X = Number of sectors in bank Bank 6 Region Information. X = Number of sectors in bank Bank 7 Region Information. X = Number of sectors in bank Bank 8 Region Information. X = Number of sectors in bank Bank 9 Region Information. X = Number of sectors in bank Bank 10 Region Information. X = Number of sectors in bank Bank 11 Region Information. X = Number of sectors in bank Bank 12 Region Information. X = Number of sectors in bank Bank 13 Region Information. X = Number of sectors in bank Bank 14 Region Information. X = Number of sectors in bank Bank 15 Region Information. X = Number of sectors in bank
0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0010h (WS256N) 0008h (WS128N) 0013h (WS256N) 000Bh (WS128N)
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16 Commonly Used Terms
Term ACC Definition ACCelerate. A special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above VCC. In some devices ACC may protect all sectors when at a low voltage. Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for 64Mbit] Least significant bit of the address input signals (A0 for all devices in this document). Operation where signal relationships are based only on propagation delays and are unrelated to synchronous control (clock) signal. Read mode for obtaining manufacturer and device information as well as sector protection status. Section of the memory array consisting of multiple consecutive sectors. A read operation in one bank, can be independent of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. Smaller size sectors located at the top and or bottom of Flash device address space. The smaller sector size allows for finer granularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. Location at the beginning or end of series of memory locations. See synchronous read. 8 bits Common Flash Interface. A Flash memory industry standard specification [JEDEC 137A and JESD68.01] designed to allow a system to interrogate the Flash to determine its size, type and other performance parameters. Zero (Logic Low Level) Special purpose register which must be programmed to enable synchronous read mode Synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address Returns bits of a Flash memory array to their default state of a logical One (High Level). Halts an erase operation to allow reading or programming in any sector that is not selected for erasure Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram for further details. Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address. Multi-Chip Package. A method of combining integrated circuits in a single package by stacking multiple die of the same or different devices. The programmable area of the product available for data storage. SpansionTM trademarked technology for storing multiple bits of data in the same transistor.
Amax Amin Asynchronous Autoselect
Bank
Boot sector Boundary Burst Read Byte CFI Clear Configuration Register
Continuous Read Erase Erase Suspend/Erase Resume
BGA
Linear Read MCP Memory Array MirrorBitTM Technology
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Term Page
Definition Group of words that may be accessed more rapidly as a group than if the words were accessed individually. Asynchronous read operation of several words in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. Different words in the group are accessed by changing only the least significant address lines. Sector protection method which uses a programmable password, in addition to the Persistent Protection method, for protection of sectors in the Flash memory device. Sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the Flash memory device. This method replaces a prior technique of requiring a 12V supply to control the protection method. Stores data into a Flash memory by selectively clearing bits of the memory array in order to leave a data pattern of ones and zeros. Halts a programming operation to read data from any location that is not selected for programming or erase. Host bus cycle that causes the Flash to output data onto the data bus. Dynamic storage bits for holding device control information or tracking the status of an operation. Secured Silicon. An area consisting of 256 bytes in which any word may be programmed once, and the entire area may be protected once from any future programming. Information in this area may be programmed at the factory or by the user. Once programmed and protected there is no way to change the secured information. This area is often used to store a software readable identification such as a serial number. Use of one or more control bits per sector to indicate whether each sector may be programmed or erased. If the Protection bit for a sector is set the embedded algorithms for program or erase ignores program or erase commands related to that sector. An Area of the memory array in which all bits must be erased together by an erase operation. Mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operation may then proceed while the host immediately follows the embedded algorithm command with reading from another bank. Reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. Operation that progresses only when a timing signal, known as a clock, transitions between logic levels (that is, at a clock edge). Separate power supply or voltage reference signal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs. Mode that facilitates faster program times by reducing the number of command bus cycles required to issue a write operation command. In this mode the initial two Unlock write cycles, of the usual 4 cycle Program command, are not required - reducing all Program commands to two bus cycles while in this mode. Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two contiguous words located on a two word boundary. A quad word is four contiguous words located on a four word boundary.
Page Read
Password Protection
Persistent Protection
Program Program Suspend/Program Resume Read Registers
Secured Silicon
Sector Protection
Sector
Simultaneous Operation
Synchronous Operation
VersatileIOTM (VIO)
Unlock Bypass
Word
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Term
Definition Special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last Byte or Word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. Interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. The term write is often associated with writing command cycles to enter or exit a particular mode of operation. Multi-word area in which multiple words may be programmed as a single operation. A Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. Method of writing multiple words, up to the maximum size of the Write Buffer, in one operation. Using Write Buffer Programming results in 8 times faster programming time than by using single word at a time programming commands. Allows the host system to determine the status of a program or erase operation by reading several special purpose register bits.
Wraparound
Write
Write Buffer
Write Buffer Programming
Write Operation Status
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1.8V pSRAM Type 4
4M x 16-bit Synchronous Burst pSRAM
ADVANCE INFORMATION
Features
Process Technology: CMOS Organization: 4M x16 bit Power Supply Voltage: 1.7~2.0V Three State Outputs Supports MRS (Mode Register Set) MRS control - MRS Pin Control Supports Power Saving modes - Partial Array Refresh mode Internal TCSR Supports Driver Strength Optimization for system environment power saving Supports Asynchronous 4-Page Read and Asynchronous Write Operation Supports Synchronous Burst Read and Asynchronous Write Operation (Address Latch Type and Low ADV# Type) Supports Synchronous Burst Read and Synchronous Burst Write Operation Synchronous Burst (Read/Write) Operation -- Supports 4 word / 8 word / 16 word and Full Page(256 word) burst -- Supports Linear Burst type & Interleave Burst type -- Latency support: Latency 5 @ 66 MHz(tCD 10ns) Latency 4 @ 54 MHz(tCD 10ns) -- Supports Burst Read Suspend in No Clock toggling -- Supports Burst Write Data Masking by /UB & /LB pin control -- Supports WAIT# pin function for indicating data availability. Max. Burst Clock Frequency: 66 MHz
Publication Number S71WS-N_01
Revision A
Amendment 4
Issue Date September 15, 2005
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17 Pin Description
Pin Name CLK ADV# MRS# CS# OE# WE# LB# UB# A0-A21 Function Clock Address Valid Mode Register set Chip Select Input Output Enable Write Enable Lower Byte (I/O0~7) Upper Byte (I/O8~15) Address 0 ~ Address 21 Type Description Commands, Data are referenced to CLK Address valid from ADV# falling edge to ADV# rising edge MRS# enables Mode Register to be set. Addresses are loaded as Mode setting is Low CS# enables the chip to start operating when Low CS# disables the chip and puts it into standby mode when High CS# stops burst operating.during burst operation when High OE# enables the chip to output the data when Low WE# enables the chip to start writing the data when Low UB# (or LB#) enables upper byte (or lower byte) to be operated when Low Valid addresses input when ADV# is low. Mode setting inputs during MRS# Low. Input/Output Power Power GND GND Output -- Depending on UB# or LB# status, word (16-bit, UB#, and LB# low) data, upper byte (8-bit, UB# low & LB# high) data or lower byte (8-bit, LB# low, and UB# high) data is loaded Power supply for cells and circuits except for I/O buffer circuits Power supply for I/O buffer circuits Ground for cells and circuits except for I/O buffer circuits Ground for I/O buffer circuits WAIT# indicates that output data is invalid when Low --
I/O0-I/O15 VCC VCCQ VSS VSSQ WAIT# DNU
Data Inputs / Outputs Core Voltage Source I/O Voltage Source Core Ground Source I/O Ground Source Valid Data Indicator Do Not Use
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18 Functional Block Diagram
CLK generator Precharge circuit.
Vcc Vss
Row Addresses
Row select
Memory array
I/O0~I/O7
Data controller Data controller Data controller
I/O Circuit Column select
I/O8~I/O15
Column Addresses
CLK
ADV# MRS# CS# OE# WE# UB# LB# WAIT# Control Logic
19 Power Up Sequence
After applying VCC up to minimum operating voltage (1.7 V), drive CS# high first and then drive MRS# high. This gets the device into power up mode. Wait for a minimum of 200 s to get into the normal operation mode. During power up mode, the standby current cannot be guaranteed. To obtain stable standby current levels, at least one cycle of active operation should be implemented regardless of wait time duration. To obtain appropriate device operation, be sure to follow the power up sequence. 1. 2. Apply power. Maintain stable power (VCC min.=1.7 V) for a minimum 200 s with CS# and MRS# high.
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20 Power Up and Standby Mode Timing Diagrams
20.1 Power Up
200 s VCC(Min) VCC Min. 0ns MRS# Min. 200 s
~
~ ~ ~ ~
CS#
Min. 0ns Power Up Mode
Normal Operation
Note: After VCC reaches VCC(Min.), wait 200 s with CS# and MRS# high. This puts the device into normal operation.
Figure 20.1
Power Up Timing
20.2 Standby Mode
CS# = VIH MRS# = VIH CS# = UB# = LB# = VIL WE# = VIL, MRS# = VIH CS# = VIL, UB# or LB# = VIL MRS# = VIH CS# = VIH
Power On
Initial State (wait 200s)
MRS Setting
Acti e v
Standby Mode
MRS# = VIH MRS# = VIL
PAR Mode
MRS Setting
CS# = VIL WE# = VIL, MRS#=VIL
Figure 20.2 Standby Mode State Machines
The default mode after power up is Asynchronous mode (4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed, so the MRS# setting sequence is highly recommended after power up. For entry to PAR mode, drive the MRS# pin into VIL for over 0.5s (suspend period) during standby mode after the MRS# setting has been completed (A4=1, A3=0). If the MRS# pin is driven into VIH during PAR mode, the device reverts to standby mode without the wake up sequence.
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21 Functional Description
Table 21.1
Mode Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set
Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0)
CS# H H L L L L L L L L L MRS# H L H H H H H H H H L OE# X X H X L L L H H H H WE# X X H X H H H L L L L LB# X X X H L H L L H L L UB# X X X H H L L H L L L I/O0-7 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z I/O8-15 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN High-Z Power Standby PAR Active Active Active Active Active Active Active Active Active
Legend: X = Don't care (must be low or high state).
Notes:
1. 2. In asynchronous mode, Clock and ADV# are ignored. The WAIT# pin is High-Z in asynchronous mode.
Table 21.2
Mode Deselected Deselected Output Disabled Outputs Disabled Read Command Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set CS# H H L L L L L L L L L L
Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1)
MRS# H L H H H H H H H H H L OE# WE# LB# UB# X (Note 1) X (Note 1) X (Note 1) H X (Note 1) H L L H L L L I/O0-7 HighZ HighZ HighZ HighZ HighZ DOUT HighZ DOUT DIN HighZ DIN HighZ I/O8-15 HighZ HighZ HighZ HighZ HighZ HighZ DOUT DOUT HighZ DIN DIN HighZ X (note 2) X (note 2) X (note 2) X (note 2) H H H CLK X (note 2) X (note 2) X (note 2) X (note 2) ADV# X (note 2) X (note 2) H H Power Standby PAR Active Active Active Active Active Active Active Active Active Active X X X (Note 1) (Note 1) (Note 1) X X X (Note 1) (Note 1) (Note 1) H H X (Note 1) H X (Note 1) L H L L H L L
X X (Note 1) (Note 1) X (Note 1) L L L H H H H H H H H L L L L
or or or or
Notes:
1. 2. 3. X must be low or high state. X means Don't care (can be low, high or toggling). WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram for Wait# pin function.
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Table 21.3
Mode Deselected Deselected Output Disabled Outputs Disabled Read Command Lower Byte Read Upper Byte Read Word Read Write Command Lower Byte Write Upper Byte Write Word Write Mode Register Set H H L L L L L L
Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0)
OE# X (Note 1) X (Note 1) H X (Note 1) X (Note 1) L L L X (Note 1) H H H WE# X (Note 1) X (Note 1) H X (Note 1) H H H H LB# X (Note 1) X (Note 1) X H X L H L UB# X (Note 1) X (Note 1) X H X H L L I/O0-7 I/O8-15 CLK ADV# Power H L H H H H H H X X High-Z High-Z Standby (Note 2) (Note 2) High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT High-Z DOUT DOUT H H H X X (Note 2) (Note 2) X (Note 2) X (Note 2) H H PAR Active Active Active Active Active Active
CS# MRS#
L L L L
H H H H
L
or X (Note 1) X (Note 1) X (Note 1) L H L H L L
High-Z High-Z DIN High-Z DIN High-Z DIN DIN H H H
Active Active Active Active
L
L
H
L
or
L
L
High-Z High-Z
Active
Notes:
1. 2. 3. 4. X must be low or high state. X means "Don't care" (can be low, high or toggling). WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram for WAIT# pin function. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
5.
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22 Mode Register Setting Operation
The device has several modes: Asynchronous Page Read mode Asynchronous Write mode Synchronous Burst Read mode Synchronous Burst Write mode Standby mode Partial Array Refresh (PAR) mode. Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS) option. The MRS option also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode.
22.1
Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of this device. It programs Partial Array Refresh (PAR), burst length, burst type, latency count and various vendor specific options to make pSRAM Type 4 useful for a variety of different applications. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS# to VIL and driving OE# to VIH during valid addressing. The mode register is divided into various fields depending on the fields of functions. The PAR field uses A0~A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Driver Strength uses A16~A17. Refer to Table 22.1 for detailed Mode Register Settings. A18~A22 addresses are Don't care in the Mode Register Setting.
Table 22.1
Address Function A17 - A16 DS
Mode Register Setting According to Field of Function
A13 WP A12 RFU A11 - A9 Latency A8 BT A7 - A5 BL A4 - A3 PAR A2 PARA A1 - A0 PARS MS
A15 - A14
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Reserved for Future Use).
Note: DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
Table 22.2
Driver Strength A17 0 0 1 A16 0 1 0 WAIT# Polarity A13 0 1 WP Low Enable (default) High Enable A12 0 1 DS Full Drive (default) 1/2 Drive 1/4 Drive RFU RFU Must (default) -- A15 0 0 1 A14 0 1 0
Mode Register Set
Mode Select MS Async. 4 Page Read / Async. Write (default) Sync. Burst Read / Async. Write Sync. Burst Read / Sync. Burst Write Burst Type A8 0 1 BT Linear (default) Interleave Burst Length A7 A6 A5 0 0 1 1 1 1 0 1 0 1 0 1 BL 4 word 8 word 16 word (default) Full (256 word)
Latency Count A11 A10 A9 0 0 0 0 0 0 1 1 0 1 0 1 Latency 3 4 5 (default) 6
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Partial Array Refresh A4 1 1 A3 0 1 PAR PAR Enable PAR Disable (default) A2 0 1
PAR Array PARA Bottom Array (default) Top Array A1 0 0 1 1 A0 0 1 0 1
PAR Size PARS Full Array (default) 3/4 Array 1/2 Array 1/4 Array
Note: The address bits other than those listed in the table above are reserved. For example, Burst Length address
bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then the mode will be set to the default mode. Each field has its own default mode as indicated. A12 is a reserved bit for future use. A12 must be set as 0. Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion. The 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500 ns. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
22.2 Mode Register Setting Timing
In this device, the MRS# pin is used for two purposes. One is to get into the mode register setting and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting, the system must drive MRS# pin to VIL and immediately (within 0.5s) issue a write command (drive CS#, ADV#, UB#, LB# and WE# to VIL and drive OE# to VIH during valid address). If the subsequent write command (WE# signal input) is not issued within 0.5s, then the device might get into the PAR mode. This device supports software access control type mode register setting timing. This timing consists of 5 cycles of Read operation. Each cycle of Read Operation is normal asynchronous read operation. Clock and ADV# are don't care and WAIT# signal is High-Z. CS# should be toggling between cycles. The address for 1st, 2nd and 3rd cycle should be 3FFFFF(h) and the address for 4th cycle should be 3FFEFF. The address for 5th cycle should be MRS code (Register setting values).
ADV#
tWC
Address
CS#
tCW tAW tBW
UB#, LB# WE#
tWP tAS tMW
Register Write Start Register Write Complete
tWU
Register Update Complete
MRS#
Figure 22.1
Pin MRS Timing Waveform (OE# = VIH)
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Address
3FFFFF tRCM
3FFFFF
3FFFFF
3FFEFF
MRS CODE
CS#
tCHM
OE#
tCLM
WE#
Notes: 1. MRS#= VIH, CLK = ADV# = UB# = LB# = Don't care, WAIT# = High-Z. 2. Do not allow this timing to occur during normal operation.
Figure 22.2 Software MRS Timing Waveform Table 22.3 MRS AC Characteristics
Symbol tMW tWU tRCM tCHM tCLM Speed Min Max 0 500 0 -- 70 -- 10 -- 60 -- Units ns ns ns ns ns
MRS
Parameter List MRS# Enable to Register Write Start End of Write to MRS# Disable Read Cycle time CS# High pulse width CS# Low pulse width
Note: VCC=1.7~2.0V, TA=-40 to 85C, Maximum Main Clock Frequency=66MHz.
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23 Asynchronous Operation
23.1 Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are driven to VIL under the valid address without toggling page addresses (A0, A1). If the page addresses (A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time (tRC) and the second, the third and the fourth data will be out with the page cycle time (tPC). (MRS# and WE# should be driven to VIH during the asynchronous (page) read operation) Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
23.2
Asynchronous Write Operation
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the valid address. MRS# and OE# should be driven to VIH during the asynchronous write operation. Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
23.3
Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the valid address. Clock input does not have any affect to the write operation (MRS# and OE# should be driven to VIH during write operation. ADV# can be either toggling for address latch or held in VIL). Clock, ADV#, and WAIT# signals are ignored during the asynchronous (page) read operation.
A22~A2 A1 ~A0 CS#
UB#, LB# OE# Data Out
Figure 23.1
Address
Asynchronous 4-Page Read
CS# UB#, LB#
WE# Data in Data out
High-Z
High-Z
HighZ
Figure 23.2 Asynchronous Write
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24 Synchronous Burst Operation
Burst mode operations enable the system to get high performance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV# (whichever occurs first). CS# should be setup before the address latch. During this first clock rising edge, WE# indicates whether the operation is going to be a Read (WE# High) or a Write (WE# Low). For the optimized Burst Mode of each system, the system should determine how many clock cycles are required for the first data of each burst access (Latency Count), how many words the device outputs during an access (Burst Length) and which type of burst operation (Burst Type: Linear or Interleave) is needed. The Wait Polarity should also be determined (See Table 22.2).
24.1
Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV# low pulse. ADV# and CS# should be set up before the clock rising. During the Read command, WE# should be held in VIH. The multiple clock risings (during the low ADV# period) are allowed, but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD.
24.2 Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV# and WE# low pulse. ADV#, WE# and CS# should be set up before the clock rising. The multiple clock risings (during the low ADV# period) are allowed but, the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK ADV# Addr. CS# UB#, LB# OE# Data Out WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 24.1
0 1 2
Synchronous Burst Read
3 4 5 6 7 8 9 10 11 12 13
CLK ADV# Addr . CS# UB#, LB# WE# Data in WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 24.2 Synchronous Burst Write
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25 Synchronous Burst Operation Terminology
25.1 Clock (CLK)
The clock input is used as the reference for synchronous burst read and write operation of the pSRAM Type 4. The synchronous burst read and write operations are synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH.
25.2 Latency Count
The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. This value depends on the input clock frequency. Table 25.1 shows the supported Latency Count.
Table 25.1 Latency Count Support
Clock Frequency Latency Count Up to 66 MHz 5 Up to 54 MHz 4 Up to 40 MHz 3
Table 25.2
Set Latency # of Clocks for 1st data (Read) # of Clocks for 1st data (Write)
T
Number of CLocks for 1st Data
Latency 3 4 2 Latency 4 5 3 Latency 5 6 4
Clock
ADV#
Address Latency 3 Data out Latency 4 Data out Latency 5 Data out Latency 6 Data out
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
Note: The first data will always keep the Latency. From the second data on, some period of wait time may be caused by WAIT# pin.
Figure 25.1
Latency Configuration (Read)
25.3
Burst Length
Burst Length identifies how many data the device outputs during an access. The device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs to meet tBC (Burst Cycle time) parameter as 2500 ns max. The first data will be output with the set Latency + tCD. From the second data on, the data will be output with tCD from each clock.
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25.4 Burst Stop
Burst stop is used when the system wants to stop burst operation on purpose. If driving CS# to VIH during the burst read operation, then the burst operation is stopped. During the burst read operation, the new burst operation cannot be issued. The new burst operation can be issued only after the previous burst operation is finished. The burst stop feature is very useful because it enables the user to utilize the unsupported burst length such as 1 burst or 2 burst, used mostly in the mobile handset application environment.
25.5 Wait Control (WAIT#)
The WAIT# signal indicates to the host system when it's data-out or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT# polarity (WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of the WAIT# signal, it should be set active one clock prior to the data regardless of Read or Write cycle.
0
CLK ADV# CS# Read Data out WAIT# Write Data in WAIT# Latency 5
1
2
3
4
5
6
7
8
9
10
11
12
13
DQ0
DQ1
DQ2
DQ3
High -Z
Latency 5 D0 D1 D2 D3
High -Z
Note: LATENCY: 5, Burst Length: 4, WP: Low Enable
Figure 25.2 WAIT# and Read/Write Latency Control
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25.6 Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in Table 25.3.
Table 25.3
Start Address 0 1 2 3 4 5 6 7 ~ 14 15 ~ 255
Burst Sequence
Wrap (Note 1)
Burst Address Sequence (Decimal) 4 word Burst Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleave 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 word Burst Linear Interleave Linear 0-1-2-...-14-15 1-2-3-...-15-0 2-3-4-...-0-1 3-4-5-...-1-2 4-5-6-...-2-3 5-6-7-...-3-4 6-7-8-...-4-5 7-8-9-...-5-6 ~ 14-15-0-...-12-13 15-0-1-...-13-14 0-1-...-5-6-7 0-1-2-...-6-7 1-2-...-6-7-0 1-0-3-...-7-6 2-3-...-7-0-1 2-3-0-...-4-5 3-4-...-0-1-2 3-2-1-...-5-4 4-5-...-1-2-3 4-5-6-...-2-3 5-6-...-2-3-4 5-4-7-...-3-2 6-7-...-3-4-5 6-7-4-...-0-1 7-0-...-4-5-6 7-6-5-...-1-0 16 word Burst Interleave 0-1-2-3-4...14-15 1-0-3-2-5...15-14 2-3-0-1-6...12-13 3-2-1-0-7...13-12 4-5-6-7-0...10-11 5-4-7-6-1...11-10 6-7-4-5-2...8-9 7-6-5-4-3...9-8 ~ 14-15-12-...-0-1 15-14-13-...-1-0 Full Page(256 word) Linear 0-1-2-...-254-255 1-2-3-...-255-0 2-3-4-...-255-0-1 3-4-5-...-255-0-1-2 4-5-6-...-255-0-1-2-3 5-6-7-...-255-...-3-4 6-7-8-...-255-...-4-5 7-8-9-...-255-...-5-6 ~ 14-15-...-255-...-12-13 15-16-...-255-...-13-14 ~ 255-0-1-...-253-254
Notes:
1. 2. Wrap: Burst Address wraps within word boundary and ends after fulfilled the burst length. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500 ns.
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26 Low Power Features
26.7 Partial Array Refresh (PAR) mode
The PAR mode enables the user to specify the active memory array size. This device consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays through the Mode Register Setting. The active memory array is periodically refreshed whereas the disabled array is not refreshed, so the previously stored data is lost. Even though PAR mode is enabled through the Mode Register Setting, PAR mode execution by the MRS# pin is still needed. The normal operation can be executed even in refresh-disabled array as long as the MRS# pin is not driven to the Low condition for over 0.5 s. Driving the MRS# pin to the High condition puts the device back to the normal operation mode from the PAR executed mode. Refer to Figure 26.1 and Table 26.1 for PAR operation and PAR address mapping.
MRS# Normal Operation MODE 0.5 s Suspend PAR mode Normal Operation
CS#
Figure 26.1 Table 26.1
Power Mode Standby (Full Array) Partial Refresh(3/4 Block) Partial Refresh(1/2 Block) Partial Refresh(1/4 Block) Address (Bottom Array) (Note 2)
PAR Mode Execution and Exit PAR Mode Characteristics
Address (Top Array) (Note 2) 000000h ~ 3FFFFFh 100000h ~ 3FFFFFh 200000h ~ 3FFFFFh 300000h ~ 3FFFFFh Valid (Note 1) Memory Cell Data Standby Current (A, Max) TBD TBD TBD TBD 0 Wait Time (s)
000000h ~ 3FFFFFh 000000h ~ 2FFFFFh 000000h ~ 1FFFFFh 000000h ~ 0FFFFFh
Notes:
1. 2. Only the data in the refreshed block are valid. The PAR Array can be selected through Mode Register Set (see Mode Register Setting Operation).
26.8 Driver Strength Optimization
The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The device supports full drive, 1/2 drive and 1/4 drive.
26.1
Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very useful tool for reducing standby current at room temperature (below 40C). DRAM cells have weak refresh characteristics in higher temperatures. High temperatures require more refresh cycles, which can lead to standby current increase. Without the internal TCSR, the refresh cycle should be set at worst condition so as to cover the high temperature (85C) refresh characteristics. But with internal TCSR, a refresh cycle below 40C can be optimized, so the standby current at room temperature can be greatly reduced. This feature is beneficial since most mobile phones are used at or below 40C in the phone standby mode.
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27 Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Power supply voltage relative to VSS Power Dissipation Storage temperature Operating Temperature Symbol VIN , VOUT VCC PD TSTG TA Ratings -0.2 V to VCC+0.3 V -0.2 V to 2.5V 1.0 -65 to 150 -40 to 85 Unit V V W C C
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Functional operation should be restricted to use under recommended operating conditions only. Exposure to absolute maximum rating conditions longer than one second may affect reliability.
28 DC Recommended Operating Conditions
Symbol VCC VSS VIH VIL
Notes:
1. 2. 3. 4. TA=-40 to 85C, unless otherwise specified. Overshoot: VCC+1.0V in case of pulse width 20ns. Undershoot: -1.0V in case of pulse width 20ns. Overshoot and undershoot are sampled, not 100% tested.
Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage
Min 1.7 0 0.8 x VCC -0.2 (note 3)
Typ 1.85 0 -- --
Max 2.0 0 VCC + 0.2 (note 2) 0.4
Unit
V
29 Capacitance (Ta = 25C, f = 1 MHz)
Symbol CIN CIO Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min -- -- Max 8 10 Unit pF pF
Note: Capacitance is sampled, not 100% tested.
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30 DC and Operating Characteristics
30.1 Common
Item Input Leakage Current Output Leakage Current Average Operating Current Average Operating Current (Sync) Output Low Voltage Output High Voltage Standby Current (CMOS) Symbol ILI ILO ICC2 ICC3 VOL VOH ISB1 (Note 2) VIN=VSS to VCC CS#=VIH, MRS#=VIH, OE#=VIH or WE#=VIL, VIO=VSS to VCC Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS#=VIL, MRS#=VIH, VIN=VIL or VIH Burst Length 4, Latency 5, 66MHz, IIO=0mA, Address transition 1 time, CS#=VIL, MRS#=VIH, VIN=VIL or VIH IOL=0.1mA IOH=-0.1mA CS# VCC-0.2V, MRS# VCC-0.2V, Other inputs = VSS to VCC < 40C < 85C 3/4 Block < 40C Partial Refresh Current MRS# 0.2V, CS# VCC-0.2V ISBP (Note 1) Other inputs = VSS to VCC < 85C 1/2 Block 1/4 Block 3/4 Block 1/2 Block 1/4 Block -- 1.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Test Conditions Min Typ -1 -1 -- -- -- -- Max 1 1 40 40 0.2 -- 120 180 120 115 115 180 165 165 A A Unit A A mA mA V V A A
Notes:
1. Full Array Partial Refresh Current (ISBP) is the same as Standby Current (ISB1). 2. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured 60 ms from the time when standby mode is set up.
31 AC Operating Conditions
31.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC -0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load (See Figure 31.1): CL=30pF
Vtt = 0.5 x VDDQ
50 Dout Z0= 50 30pF
Figure 31.1
PAR Mode Execution and Exit
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31.2
Asynchronous AC Characteristics
(VCC=1.7~2.0V, TA=-40 to 85 C)
Symbol tRC tPC tAA tPA Read Cycle Time Page Read Cycle Time Address Access Time Page Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold Write Cycle Time Chip Select to End of Write ADV# Minimum Low Pulse Width Address Set-up Time to Beginning of Write Address Set-up Time to ADV# Falling Address Hold Time from ADV# Rising CS# Setup Time to ADV# Rising Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width WE# High Pulse Width Write Recovery Time WE# Low to Read Latency Data to Write Time Overlap Data Hold from Write Time Parameter Speed Min 70 25 -- -- -- -- -- 10 5 5 0 0 0 3 70 60 7 0 0 7 10 60 60 55 (Note 1) 5 ns 0 1 30 0 Max -- -- 70 20 70 35 35 -- -- -- 12 12 12 -- -- -- -- -- -- -- -- -- -- -- Latency-1 clock -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- ns clock ns ns
Aysnc (Page) Read
tCO tOE tBA tLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tWC tCW tADV tAS tAS(A) tAH(A) tCSS(A) tAW tBW tWP tWHP tWR tWLRL tDW tDH
Note: tWP (min)=70ns for continuous write operation over 50 times.
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31.3
Timing Diagrams
31.3.1 Asynchronous Read Timing Waveform
MRS# = VIH, WE# = VIH, WAIT# = High-Z
tRC
Address
tAA
CS#
tOH
tCO tCHZ
UB#, LB#
tBA tBHZ
OE#
tOE tOLZ tBLZ tLZ tOHZ Data Valid
Data out
High-Z
Notes:
1. 2. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. In asynchronous read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 31.2 Timing Waveform Of Asynchronous Read Cycle Table 31.1
Speed Symbol tRC tAA tCO tBA tOE tOH Min 70 -- -- -- -- 3 Max -- 70 70 35 35 -- Units Symbol tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Min 5 5 10 0 0 0
Asynchronous Read AC Characteristics
Speed Max -- -- -- 7 7 7 Units
ns
ns
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31.3.1.1 Page Read MRS# = VIH, WE# = VIH, WAIT# = High-Z
tRC A22~A2 tAA A1~A0
Valid Address Valid Address Valid Address Valid Address Valid Address
tOH
tCO CS# tBA UB#, LB# tOE OE# tLZ High Z tOLZ tBLZ
tPC
tBHZ
tPA
Dat a Valid Dat a Valid Dat a Valid Dat a Valid
tCHZ tOHZ
Data out
Notes:
1. 2. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. In asynchronous 4 page read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 31.3 Timing Waveform Of Page Read Cycle Table 31.2
Speed Symbol tRC tAA tPC tPA tCO tBA tOE Min 70 -- 25 -- -- -- -- Max -- 70 -- 20 70 35 35 Units Symbol tOH tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Min 3 5 5 10 0 0 0
Asynchronous Page Read AC Characteristics
Speed Max -- -- -- -- 7 7 7 Units
ns
ns
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31.3.2
Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
tWC Address tAW tCW tWR tCSHP tAW tCW tWR tWC
CS#
tBW UB#, LB# tWP WE# tAS tDH tDW Dat Valid a High-Z tWHP tAS
tBW
tWP
Data in Data out
tDH tDW Dat Valid a HighZ
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored. Condition for continuous write operation over 50 times: tWP(min)=70ns.
2. 3. 4. 5. 6.
Figure 31.4 Timing Waveform Of Write Cycle Table 31.3
Symbol tWC tCW tAW tBW tWP Speed Min 70 60 60 60 55 (note 1)
Asynchronous Write AC Characteristics
Max -- -- -- -- -- Units Symbol tAS tWR tDW tDH tCHSP Min 0 0 30 0 10 Speed Max -- -- -- -- Units
ns
ns
Note: tWP(min) = 70ns for continuous write operation over 50 times.
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31.3.2.1 Write Cycle 2 MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
tWC Address tCW CS# tAW UB#, LB# tBW tAS tWP WE# tDW Data in Dat Valid a tDH tWR
Data out
High-Z
HighZ
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
2. 3. 4. 5.
Figure 31.5 Timing Waveform of Write Cycle(2) Table 31.4
Symbol tWC tCW tAW tBW tWP
Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed Min 70 60 60 60 55 (note 1) Max -- -- -- -- -- Units Symbol tAS tWR tDW tDH Speed Min Max 0 0 30 0 -- -- -- -- Units
ns
ns
Note: tWP(min) = 70ns for continuous write operation over 50 times.
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31.3.2.1 Write Cycle (Address Latch Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0 CLK tADV ADV# Address CS# UB#, LB# tWLRL WE# tAS Data in Read Latency 5 Data out HighZ High-Z tAS(A)
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(A) tCSS(A) tCW tAW tBW tWP tDW Dat Valid a tDH
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. tCW is measured from the CS# going low to the end of write. tBW is measured from the UB# and LB# going low to the end of write. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
2. 3. 4. 5.
Figure 31.6 Timing Waveform Of Write Cycle (Address Latch Type) Table 31.5
Symbol tADV tAS(A) tAH(A) tCSS(A) tCW tAW
Notes:
1. 2. Address Latch Type, WE# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Max -- -- -- -- -- -- Units Symbol tBW tWP tWLRL tAS tDW tDH Speed Min 60 55 (note 2) 1 0 30 0 Max -- -- -- -- -- -- Units ns clock ns
Min 7 0 7 10 60 60
ns
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31.3.3
Asynchronous Write Timing Waveform in Synchronous Mode
31.3.3.1 Write Cycle (Address Latch Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# and LB# Controlled
0 CLK tADV ADV# Address CS# UB#, LB# WE# Data in Read La tency 5 Data out High-Z High-Z tAS(A)
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(A) tCSS(A)
tCW tAW tBW
tAS
tWLRL
tWP tDW Dat Valid a tDH
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation. A write ends at the earliest transition when CS# goes or and WE# goes high. The tWP is measured from the beginning of write to the end of write. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. tCW is measured from the CS# going low to the end of write. tBW is measured from the UB# and LB# going low to the end of write. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
2. 3. 4. 5.
Figure 31.7 Timing Waveform Of Write Cycle (Low ADV# Type) Table 31.6
Symbol tADV tAS(A) tAH(A) tCSS(A) tCW tAW
Notes:
1. 2. Address Latch Type, UB#, LB# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Max -- -- -- -- -- -- Units Symbol tBW tWP tWLRL tAS tDW tDH Speed Min 60 55 (Note 2) 1 0 30 0 Max -- -- -- -- -- -- Units ns ns clock ns
Min 7 0 7 10 60 60
ns
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31.3.4
Asynchronous Write Timing Waveform in Synchronous Mode
31.3.4.1 Write Cycle (Low ADV# Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0 CLK ADV# tWC Address tCW CS# UB#, LB# tWLRL WE# Data in Read Latency 5 Data out High-Z HighZ tAS tDH tDW Dat Valid a tAW tBW tWP tWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
2. 3. 4. 5.
Figure 31.8 Timing Waveform Of Write Cycle (Low ADV# Type) Table 31.7
Symbol tWC tCW tAW tBW tWP
Notes:
1. 2. Low ADV# Type, WE# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Min 70 60 60 60 55 (note 2) Max -- -- -- -- -- Units Symbol tWLRL tAS tWR tDW tDH Min 1 0 0 30 0 Speed Max -- -- -- -- -- Units clock
ns
ns
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31.3.4.2 Write Cycle (Low ADV# Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
0 CLK ADV# tWC Address tCW CS# UB#, LB# WE# Data in Read Latency 5 Data out High-Z HighZ tAW tBW tAS tWLRL tWP tDH tDW Data Valid tWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
2. 3. 4. 5.
Figure 31.9 Timing Waveform Of Write Cycle (Low ADV# Type) Table 31.8
Symbol tWC tCW tAW tBW tWP
Notes:
1. 2. Low ADV# type multiple write, UB#, LB# controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Min 70 60 60 60 55 (note 2) Max -- -- -- -- -- Units Symbol tWLRL tAS tWR tDW tDH Speed Min Max 1 -- 0 -- 0 -- 30 -- 0 -- Units clock
ns
ns
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31.3.4.3 Multiple Write Cycle (Low ADV# Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
ADV# tWC Address tAW tCW tWR tAW tCW tWR tWC
CS#
tBW UB#, LB# tWP WE# tAS tDH tDW Data Valid High-Z tWHP tAS
tBW
tWP
Data in Data out
tDH tDW Dat Valid a High-Z
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. Clock input does not have any affect on the asynchronous multiple write operation if tWHP is shorter than the (Read Latency - 1) clock duration. tWP(min) = 70ns for continuous write operation over 50 times.
2. 3. 4. 5. 6.
Figure 31.10 Timing Waveform Of Multiple Write Cycle (Low ADV# Type) Table 31.9
Symbol tWC tCW tAW tBW tWP
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Max -- -- -- -- -- ns Units Symbol tWHP tAS tWR tDW tDH Speed Min 5ns 0 0 30 0 Max Latency-1 clock -- -- -- -- ns Units --
Min 70 60 60 60 55 (note 2)
Notes:
1. 2. Low ADV# type multiple write, WE# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
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32 AC Operating Conditions
32.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load (See Figure 32.1): CL = 30pF
Vtt = 0.5 x VDDQ
50 Dout Z0= 50 30pF
Figure 32.1
AC Output Load Circuit
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32.2
Synchronous AC Characteristics
Parameter List Clock Cycle Time Burst Cycle Time Address Set-up Time to ADV# Falling (Burst) Address Hold Time from ADV# Rising (Burst) ADV# Setup Time ADV# Hold Time CS# Setup Time to Clock Rising (Burst) Burst Operation (Common) Burst End to New ADV# Falling Burst Stop to New ADV# Falling CS# Low Hold Time from Clock CS# High Pulse Width ADV# High Pulse Width Chip Select to WAIT# Low ADV# Falling to WAIT# Low Clock to WAIT# High Chip De-select to WAIT# High-Z UB#, LB# Enable to End of Latency Clock Output Enable to End of Latency Clock UB#, LB# Valid to Low-Z Output Output Enable to Low-Z Output Burst Read Operation Latency Clock Rising Edge to Data Output Output Hold Burst End Clock to Output High-Z Chip De-select to Output High-Z Output Disable to Output High-Z UB#, LB# Disable to Output High-Z WE# Set-up Time to Command Clock WE# Hold Time from Command Clock WE# High Pulse Width UB#, LB# Set-up Time to Clock Burst Write Operation UB#, LB# Hold Time from Clock Byte Masking Set-up Time to Clock Byte Masking Hold Time from Clock Data Set-up Time to Clock Data Hold Time from Clock Symbol T tBC tAS(B) tAH(B) tADVS tADVH tCSS(B) tBEADV tBSADV tCSLH tCSHP tADHP tWL tAWL tWH tWZ tBEL tOEL tBLZ tOLZ tCD tOH tHZ tCHZ tOHZ tBHZ tWES tWEH tWHP tBS tBH tBMS tBMH tDS tDHC Speed Min 15 -- 0 7 5 7 5 7 12 7 5 5 -- -- -- -- 1 1 5 5 -- 3 -- -- -- -- 5 5 5 5 5 7 7 5 3 Max 200 2500 -- -- -- -- -- -- -- -- -- -- 10 10 12 7 -- -- -- -- 10 -- 10 7 7 7 -- -- -- -- -- -- -- -- -- ns ns clock clock ns Units
Note: (VCC = 1.7~2.0V, TA=-40 to 85 C, Maximum Main Clock Frequency = 66MHz.
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32.3
Timing Diagrams
Synchronous Burst Operation Timing Waveform
Latency = 5, Burst Length = 4 (MRS# = VIH)
0 T CLK tADVH tADVS ADV# tBEADV tAS(B) Address
Valid
32.3.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tAH(B)
Don't Ca re
tBEADV
Valid
tCSS(B) CS#
tBC
Data out
Undefined
DQ0
DQ1
DQ2
DQ3
Data in
D0
D1
D2
D3
D0
Burst Command Clock
Burst Read End Clock Burst Write End Clock
Figure 32.2 Timing Waveform Of Basic Burst Operation Table 32.1
Speed Symbol T tBC tADVS tADVH Min 15 -- 5 7 Max 200 2500 -- -- Units Symbol tAS(B) tAH(B) tCSS(B) tBEADV Min 0 7 5 7
Burst Operation AC Characteristics
Speed Max -- -- -- -- Units
ns
ns
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32.3.2
Synchronous Burst Read Timing Waveforms
32.3.2.1 Read Timings Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH). CS# Toggling Consecutive Burst Read
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tBEADV tAH(B)
Don't Ca re Valid
tCSS(B) CS#
tBC
tCSHP
tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tWH tOEL tCD
Undefined
tBHZ
tOHZ tCHZ tHZ DQ2 DQ3 tWZ tWL tWH
tOH DQ0 DQ1
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge). Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 32.3 Timing Waveform of Burst Read Cycle (1) Table 32.2
Speed Symbol tCSHP tBEL tOEL tBLZ tOLZ tHZ tCHZ Min 5 1 1 5 5 -- -- Max -- -- -- -- -- 10 7 Units ns clock Symbol tOHZ tBHZ tCD tOH tWL tWH tWZ Min -- -- -- 3 -- -- --
Burst Read AC Characteristics
Speed Max 7 7 10 -- 10 12 7 Units
ns
ns
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Information
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH). CS# Low Holding Consecutive Burst Read
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tBEADV tAH(B)
Don't Care Valid
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tOEL
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tHZ tAWL tWH
tWH
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge). Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and address. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4. 5.
Figure 32.4 Timing Waveform of Burst Read Cycle (2) Table 32.3
Speed Symbol tBEL tOEL tBLZ tOLZ tHZ Min 1 1 5 5 -- Max -- -- -- -- 10 Units clock Symbol tCD tOH tWL tAWL tWH Min -- 3 -- -- --
Burst Read AC Characteristics
Speed Max 10 -- 10 10 12 Units
ns
ns
132
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Advance
Information
Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH). Last data sustaining
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(B)
Don't C are
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tOEL
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tWH
Notes:
1. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge). Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
2. 3.
Figure 32.5 Timing Waveform of Burst Read Cycle (3) Table 32.4
Speed Symbol tBEL tOEL tBLZ tOLZ Min 1 1 5 5 Max -- -- -- -- Units clock ns Symbol tCD tOH tWL tWH Min -- 3 -- --
Burst Read AC Characteristics
Speed Max 10 -- 10 12 Units
ns
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Information
32.3.2.1 Write Timings Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH). CS# Toggling Consecutive Burst Write
0 T CLK tADVH tADVS ADV# tAS(B) Address tCSS(B) CS# tBS LB#, UB# tWEH WE# tWES tDS Latency 5 Data in tWL WAIT# High-Z tWH tDHC D0 D1 D2 tDHC D3 tWZ tWL tWH Latency 5 D0 tWHP tBH tBMS tBMH
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tBEADV tAH(B)
Don't Ca re Valid
tBC
tCSHP
Notes:
1. 2. 3. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) D2 is masked by UB# and LB#. Burst Cycle Time (tBC) should not be over 2.5s.
4. 5.
Figure 32.6 Timing Waveform of Burst Write Cycle (1) Table 32.5
Speed Symbol tCSHP tBS tBH tBMS tBMH tWES tWEH Min 5 5 5 7 7 5 5 Max -- -- -- -- -- -- -- ns Units Symbol tWHP tDS tDHC tWL tWH tWZ Min 5 5 3 -- -- --
Burst Write AC Characteristics
Speed Max -- -- -- 10 12 7 ns Units
134
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
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Information
Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH). CS# Low Holding Consecutive Burst Write
0 T CLK tADVH tADVS ADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tAH(B)
Don't Ca re
tBEADV
Valid
tCSS(B) CS#
tBC tBS tBMS
tBH
tBMH tWHP
LB#, UB# tWEH WE# tWES tDS Latency 5 Data in tWL WAIT# High-Z tWH tDHC D0 D1 D2 tDHC D3 tAWL tWH Latency 5 D0
Notes:
1. 2. 3. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) D2 is masked by UB# and LB#. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and address. Burst Cycle Time (tBC) should not be over 2.5s.
4. 5. 6.
Figure 32.7 Timing Waveform of Burst Write Cycle (2) Table 32.6
Symbol tBS tBH tBMS tBMH tWES tWEH Speed Min 5 5 7 7 5 5 Max -- -- -- -- -- -- ns
Burst Write AC Characteristics
Units Symbol tWHP tDS tDHC tWL tAWL tWH Speed Min 5 5 3 -- -- -- Max -- -- -- 10 10 12 ns Units
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Information
32.3.3
Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(B)
Don't C are
tBSADV
Valid
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data tWL WAIT# High-Z tOEL tCD
Undefined
tCSHP tCSLH
tOH DQ0 DQ1
tCHZ
tWZ tWH HighZ
tWL
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. The burst stop operation should not be repeated for over 2.5s.
3. 4.
Figure 32.8 Timing Waveform of Burst Read Stop by CS# Table 32.7
Symbol tBSADV tCSLH tCSHP tBEL tOEL tBLZ tOLZ Speed Min 12 7 5 1 1 5 5 Max -- -- -- -- -- -- -- clock ns ns
Burst Read Stop AC Characteristics
Units Symbol tCD tOH tCHZ tWL tWH tWZ Speed Min -- 3 -- -- -- -- Max 10 -- 7 10 12 7 ns Units
136
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Advance
Information
32.3.4
Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= VIH, MRS# = VIH).
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tAH(B)
Don't Ca re
tBSADV
Valid
tCSS(B) CS# tBS tCSLH tBH
tCSHP
LB#, UB#
tWEH tWES tDS Latency 5 Data in tWL WAIT# High-Z tWH D0 tDHC D1 tWZ tWL High-Z tWH Latency 5 D0 D1 D2 tWHP
WE#
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. The burst stop operation should not be repeated for over 2.5s.
3. 4.
Figure 32.9 Timing Waveform of Burst Write Stop by CS# Table 32.8
Symbol tBSADV tCSLH tCSHP tBS tBH tWES tWEH Speed Min 12 7 5 5 5 5 5 Max -- -- -- -- -- -- -- ns
Burst Write Stop AC Characteristics
Units Symbol tWHP tDS tDHC tWL tWH tWZ Speed Min 5 5 3 -- -- -- Max -- -- -- 10 12 7 ns Units
September 15, 2005 S71WS-N_01_A4
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Information
32.3.5
Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
1 0
11
tAH(B)
Don't Ca re
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tWH tOEL
tBC
tCD
Undefined
tOHZ DQ0 DQ1
tOLZ High-Z DQ1
tOH DQ2 DQ3
tHZ tWZ
Notes:
1. 2. If the clock input is halted during burst read operation, the data output is suspended. During the burst read suspend period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data is output first. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during suspend period, the previous data is sustained. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 32.10 Timing Waveform of Burst Read Suspend Cycle (1) Table 32.9
Symbol tBEL tOEL tBLZ tOLZ tCD tOH Speed Min 1 1 5 5 -- 3 Max -- -- -- -- 10 -- ns
Burst Read Suspend AC Characteristics
Units clock Symbol tHZ tOHZ tWL tWH tWZ Speed Min -- -- -- -- -- Max 10 7 10 12 7 ns Units
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Information
33 Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4 (MRS# = VIH).
0 T CLK tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21
tADVH tADV tAH(A)
tAH(B)
Don't Ca re
tBEADV tAS(A)
Valid
tCSS(B) CS#
tBC
tCSS(A) tWLRL
tAW tCW tWP
WE# tAS tOEL OE# tBEL LB#, UB# tBW tDW Data in Latency 5 Data out High -Z tWL WAIT# High-Z tWH tCD tOH
DQ0 DQ1 DQ2 DQ3
tDH
Data Valid tHZ HighZ tWZ High-Z Read Laten 5 cy
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 33.1 Table 33.1
Symbol tBEADV
Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Speed Min 7 Max -- Units ns Symbol tWLRL Speed Min 1 Max -- Units clock
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Advance
Information
Latency = 5, Burst Length = 4 (MRS# = VIH).
1 T CLK tADVS ADV# tAS(B) Address
Valid
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
18 19 20 21
tADVH
tAH(B)
Don't Ca re
tBEADV
Valid Addr ss e
tCSS(B) CS# tBC
tAW tCW tWLRL
tWR
tWP
WE# tOEL
tAS
OE#
tBEL LB#, UB#
tBW tDW tDH
Data in Latency 5 Data out High-Z tWL WAIT# High-Z tWH tCD tOH
DQ0 DQ1 DQ2 DQ3
Dat Valid a tHZ High-Z
tWZ High-Z Read Late ncy 5
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 33.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type) Table 33.2
Symbol tBEADV
Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
Speed Min 7 Max -- Units ns Symbol tWLRL Speed Min 1 Max -- Units clock
140
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Advance
Information
Latency = 5, Burst Length = 4 (MRS# = VIH).
0 CLK tADVS ADV# tAS(A) Address
Valid
1
2
3
4
5
6
7
8
9
10
11 T
12 13
14 15 16 17 18 19
20
tADVH
tADV tAH(A)
Don't Ca re
tAS(B)
tAH(B)
Don't Ca re
Valid
tCSS(A) CS#
tAW tCW tWLRL
tCSS(B)
tBC
WE# tAS OE#
tWP tOEL
tBW LB#, UB# tDW Data in tDH
tBEL
Dat Valid a Latency 5 tCD tWH tOH
DQ0 DQ1 DQ2 DQ3
tHZ tWZ
Data out
HighZ Read Latency 5 HighZ
tWL
WAIT#
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 33.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing Table 33.3
Symbol tWLRL
Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
Speed Min 1 Max -- Units clock Symbol Speed Min Max Units
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Information
Latency = 5, Burst Length = 4 (MRS# = VIH).
0 CLK tADVS tADHP ADV# tWC Address
Valid
1
2
3
4
5
6
7
8
9
10
11 T
12 13
14 15 16 17 18 19
20
tADVH
tAS(B)
tAH(B)
Don't Ca re
Valid
CS# tWLRL WE# tAS OE#
tAW tCW
tWR
tCSS(B)
tBC
tWP
tOEL
LB#, UB#
tBW tDW tDH
tBEL
Data in
Dat Valid a Latency 5 tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out
HighZ tWL tWH
tWZ
WAIT#
HighZ Read Latency 5
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 33.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing Table 33.4
Symbol tWLRL
Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed Min 1 Max -- Units clock Symbol tADHP Speed Min 5 Max -- Units ns
142
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
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Information
Latency = 5, Burst Length = 4 (MRS# = VIH).
0 T CLK tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21
tADVH tBEADV tAH(B)
Don't Ca re
tAS(B)
Valid
tAH(B)
tCSS(B) CS#
tBC tWES
tCSS(B)
tBC
tWEH
WE# tOEL OE# tBEL LB#, UB# Latency 5 Data in Latency 5 Data out HighZ High -Z tWL WAIT# tWH tCD High -Z tOH
DQ0 DQ1 DQ2 DQ3 D0 D1 D2
tBS tBH tDS
D3
tDHC
tHZ HighZ tWL tWH tWZ tWZ
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 33.5 Synchronous Burst Read to Synchronous Burst Write Timing Table 33.5
Symbol tBEADV
Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed Min 7 Max -- Units ns Symbol Speed Min Max Units
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Information
Latency = 5, Burst Length = 4 (MRS# = VIH).
0 T CLK tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21
tADVH tBEADV tAH(B)
Don't Ca re
tAS(B)
Valid
tAH(B)
tCSS(B) CS# tWES WE# tWEH
tBC
tCSS(B)
tBC
tOEL OE# tBS tBH LB#, UB# Latency 5 Data in
D0 D1 D2
tBEL tDS
D3
tDHC HighZ Latency 5 tCD tWH tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out tWL WAIT# High-Z tWH
High-Z tWZ tWL
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 33.6 Synchronous Burst Write to Synchronous Burst Read Timing Table 33.6
Symbol tBEADV
Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed Min 7 Max -- Units ns Symbol Speed Min Max Units
144
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
1.8V pSRAM Type 4
8M x 16-bit Synchronous Burst pSRAM
ADVANCE INFORMATION
Features
Process Technology: CMOS Organization: 8M x16 bit Power Supply Voltage: 1.7-2.0V Three State Outputs Supports MRS (Mode Register Set) MRS control - MRS Pin Control Supports Power Saving modes - Partial Array Refresh mode Internal TCSR Supports Driver Strength Optimization for system environment power saving Supports Asynchronous 4-Page Read and Asynchronous Write Operation Supports Synchronous Burst Read and Asynchronous Write Operation (Address Latch Type and Low ADV Type) Supports Synchronous Burst Read and Synchronous Burst Write Operation Synchronous Burst (Read/Write) Operation -- Supports 4 word / 8 word / 16 word and Full Page(256 word) burst -- Supports Linear Burst type & Interleave Burst type -- Latency support: Latency 5 @ 66MHz(tCD 10ns) Latency 4 @ 54MHz(tCD 10ns) -- Supports Burst Read Suspend in No Clock toggling -- Supports Burst Write Data Masking by /UB & /LB pin control -- Supports WAIT pin function for indicating data availability. Max. Burst Clock Frequency: 66MHz
Publication Number S71WS-N_01
Revision A
Amendment 4
Issue Date September 15, 2005
Advance
Information
34 Pin Description
Pin Name CLK ADV# MRS# CS# OE# WE# LB# UB# A0-A22 Function Clock Address Valid Mode Register set Chip Select Output Enable Write Enable Upper Byte (I/O8-15) Address 0 Lower Byte (I/O0-7) Input Type Description Commands are referenced to CLK Valid Address is latched by ADV falling edge MRS# low enables Mode Register to be set CS# low enables the chip to be active CS# high disables the chip and puts it into standby mode OE# low enables the chip to output the data WE# low enables the chip to start writing the data UB# (LB#) low enables upper byte (lower byte) to start operating Valid addresses input when ADV is low Mode setting input when MRS is low Input/Output Power Power GND GND Output Depending on UB# or LB# status, word (16-bit, UB#, and LB# low) data, upper byte (8-bit, UB# low & LB# high) data or lower byte (8-bit, LB# low, and UB# high) data is loaded Core Power supply I/O Power supply Core ground Source I/O Ground Source WAIT# indicates whether data is valid or not
- Address 22
I/O0-I/O15 VCC VCCQ VSS VSSQ WAIT#
Data Inputs / Outputs Voltage Source Voltage Source Ground Source I/O Ground Source Valid Data Indicator
35 Power Up Sequence
After applying VCC up to minimum operating voltage (1.7V), drive CS# high first and then drive MRS# high. This gets the device into power up mode. Wait 200 s minimum to get into the normal operation mode. During power up mode, the standby current cannot be guaranteed. To obtain stable standby current levels, at least one cycle of active operation should be implemented regardless of wait time duration. To obtain appropriate device operation, be sure to follow the proper power up sequence. 1. 2. Apply power. Maintain stable power (VCC min.=1.7V) for a minimum 200 s with CS# and MRS# high.
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36 Power Up and Standby Mode Timing Diagrams
36.1 Power Up
200 s VCC(Min) VCC Min. 0ns MRS# Min. 200 s
~
~ ~ ~ ~
CS#
Min. 0ns Power Up Mode
Normal Operation
Note: After VCC reaches VCC(Min.), wait 200 s with CS# and MRS# high. This puts the device into normal operation.
Figure 36.1
Power Up Timing
36.2 Standby Mode
CS# = VIH MRS# = VIH CS# = UB# = LB# = VIL WE# = VIL, MRS# = VIL CS# = VIL, UB# or LB# = VIL MRS# = VIH CS# = VIH
Power On
Initial State (wait 200s)
MRS Setting
Acti e v
Standby Mode
MRS# = VIH MRS# = VIL
PAR Mode
MRS Setting
CS# = VIL WE# = VIL, MRS#=VIL
Figure 36.2 Standby Mode State Machines
The default mode after power up is Asynchronous mode (4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed, so the MRS# setting sequence is highly recommended after power up. For entry to PAR mode, drive the MRS# pin into VIL for over 0.5s or longer (suspend period) during standby mode after the MRS# setting has been completed (A4=1, A3=0). If the MRS# pin is driven into VIH during PAR mode, the device reverts to standby mode without the wake up sequence.
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37 Functional Description
Table 37.1
Mode Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set
Asynchronous 4 Page Read & Asynchronous Write Mode (A15/A14=0/0)
CS# H H L L L L L L L L L MRS# H L H H H H H H H H L OE# X X H X L L L H H H H WE# X X H X H H H L L L L LB# X X X H L H L L H L L UB# X X X H H L L H L L L I/O0-7 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z I/O8-15 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN High-Z Power Standby PAR Active Active Active Active Active Active Active Active Active
Legend: X = Don't care (must be low or high state).
Notes:
1. 2. In asynchronous mode, Clock and ADV# are ignored. The WAIT# pin is High-Z in asynchronous mode.
Table 37.2
Mode Deselected Deselected Output Disabled Outputs Disabled Read Command Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set
Synchronous Burst Read & Asynchronous Write Mode (A15/A14=0/1)
CS# H H L L L L L L L L L L MRS# H L H H H H H H H H H L OE# X X H X X L L L H H H H WE# X X H X H H H H L L L L LB# X X X H X L H L L H L L UB# X X X H X H L L H L L L I/O0-7 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z I/O8-15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN High-Z X (note 2) X (note 2) X (note 2) X (note 2) H H H CLK X (note 2) X (note 2) X (note 2) X (note 2) ADV# X (note 2) X (note 2) H H Power Standby PAR Active Active Active Active Active Active Active Active Active Active
or or or or
Notes:
1. 2. 3. X must be low or high state. X means "Don't care" (can be low, high or toggling). WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram for Wait# pin function.
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Table 37.3
Mode Deselected Deselected Output Disabled Outputs Disabled Read Command Lower Byte Read Upper Byte Read Word Read
Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0)
CS# MRS# H H L L L L L L H L H H H H H H OE# X (note1) X (note1) H X (note1) X (note1) L L L X (note1) H H H WE# X (note1) X (note1) H X (note1) H H H H LB# UB# I/O0-7 I/O8-15 CLK ADV# Power X X X X High-Z High-Z Standby (note1) (note1) (note 2) (note 2) X X X X High-Z High-Z (note1) (note1) (note 2) (note 2) X H X L H L X H X H L L High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT High-Z DOUT DOUT H H H X (note 2) X (note 2) H H PAR Active Active Active Active Active Active
Write Command Lower Byte Write Upper Byte Write Word Write Mode Register Set
L L L L
H H H H
L
or X (note1) X (note1) X (note1) L H L H L L
High-Z High-Z DIN High-Z DIN High-Z DIN DIN H H H
Active Active Active Active
L
L
H
L
or
L
L
High-Z High-Z
Active
Notes:
1. 2. 3. X must be low or high state. X means "Don't care" (can be low, high or toggling). WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing diagram for WAIT# pin function.
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38 Mode Register Setting Operation
The device has several modes: Asynchronous Page Read mode Asynchronous Write mode Synchronous Burst Read mode Synchronous Burst Write mode Standby mode and Partial Array Refresh (PAR) mode. Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS) option. The MRS option also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode.
38.1
Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of the pSRAM. It programs Partial Array Refresh (PAR), burst length, burst type, latency count and various vendor specific options to make pSRAM useful for a variety of different applications. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS# to VIL and driving OE# to VIH during valid addressing. The mode register is divided into various fields depending on the fields of functions. The PAR field uses A0-A4, Burst Length field uses A5-A7, Burst Type uses A8, Latency Count uses A9-A11, Wait Polarity uses A13, Operation Mode uses A14-A15 and Driver Strength uses A16-A17. Refer to the Table below for detailed Mode Register Settings. A18-A22 addresses are "Don't care" in the Mode Register Setting.
Table 38.1
Address Function A17 - A16 DS
Mode Register Setting According to Field of Function
A13 WP A12 RFU A11 - A19 Latency A8 BT A7 - A5 BL A4 - A3 PAR A2 PARA A1 - A0 PARS MS
A15 - A14
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Reserved for Future Use).
Note: DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
Table 38.2
Driver Strength A17 0 0 1 A16 0 1 0 WAIT# Polarity A13 0 1 WP Low Enable (note 1) High Enable A12 0 1 DS Full Drive (note 1) 1/2 Drive 1/4 Drive RFU RFU Must (note 1) -- A15 0 0 1 A14 0 1 0
Mode Register Set
Mode Select MS Async. 4 Page Read / Async. Write (note 1) Sync. Burst Read / Async. Write Sync. Burst Read / Sync. Burst Write Burst Type BT Linear (note 1) Interleave Burst Length A7 A6 A5 0 0 1 1 1 1 0 1 0 1 0 1 BL 4 word 8 word 16 word (note 1) Full (256 word)
Latency Count A11 A10 A9 Latency A8 0 0 0 0 0 0 1 1 0 1 0 1 3 4 5 6 0 1
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Partial Array Refresh A4 1 1 A3 0 1 PAR PAR Enable PAR Disable (note 1) A2 0 1
PAR Array PARA Bottom Array (note 1) Top Array A1 0 0 1 1 A0 0 1 0 1
PAR Size PARS Full Array (note 1) 3/4 Array 1/2 Array 1/4 Array
Note: Default mode. The address bits other than those listed in the table above are reserved. For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then the mode will be set to the default mode. Each field has its own default mode, but this default mode is not 100% guaranteed, so the MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as "0". Not all the mode settings are tested. Per the mode settings to be tested, please contact Spansion. The 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.
38.2 MRS Pin Control Type Mode Register Setting Timing
In this device, the MRS pin is used for two purposes. One is to get into the mode register setting and the other is to execute Partial Array Refresh mode. To get into the Mode Register Setting, the system must drive the MRS# pin to VIL and immediately (within 0.5s) issue a write command (drive CS#, ADV#, UB#, LB# and WE# to VIL and drive OE# to VIH during valid address). If the subsequent write command (WE# signal input) is not issued within 0.5s, then the device may get into the PAR mode.
0
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV#
tWC
Address
tCW
CS#
tAW tBW
UB#, LB#
tWP
WE#
tAS tMW tWU
MRS#
Register Update Complete Register Write Complete
Register Write Start
(MRS SETTING TIMING) 1. Clock input is ignored.
Figure 38.1
Mode Register Setting Timing (OE# = VIH) MRS AC Characteristics
Symbol tMW tWU Speed Min Max 0 500 0 -- Units ns ns
Table 38.3
MRS
Parameter List MRS# Enable to Register Write Start End of Write to MRS# Disable
Note: VCC=1.7-2.0V, TA=-40 to 85C, Maximum Main Clock Frequency=66MHz
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39 Asynchronous Operation
39.1 Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are driven to VIL under the valid address without toggling page addresses (A0, A1). If the page addresses (A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time (tRC) and the second, the third and the fourth data will be out with the page cycle time (tPC). (MRS# and WE# should be driven to VIH during the asynchronous (page) read operation) Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
39.2 Asynchronous Write Operation
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the valid address. MRS# and OE# should be driven to VIH during the asynchronous write operation. Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
39.3
Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS#, WE# and UB# or LB# are driven to VIL under the valid address. Clock input does not have any affect to the write operation (MRS# and OE# should be driven to VIH during write operation. ADV# can be either toggling for address latch or held in VIL). Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
A22~A2 A1 ~A0 CS#
UB#, LB# OE# Data Out
Figure 39.1
Address
Asynchronous 4-Page Read
CS# UB#, LB#
WE# Data in Data out
High-Z
High-Z
HighZ
Figure 39.2 Asynchronous Write
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40 Synchronous Burst Operation
Burst mode operations enable the system to get high performance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV# (whichever occurs first). CS# should be setup before the address latch. During this first clock rising edge, WE# indicates whether the operation is going to be a Read (WE# High) or a Write (WE# Low). For the optimized Burst Mode of each system, the system should determine how many clock cycles are required for the first data of each burst access (Latency Count), how many words the device outputs during an access (Burst Length) and which type of burst operation (Burst Type: Linear or Interleave) is needed. The Wait Polarity should also be determined (See Table 38.2).
40.1
Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV# low pulse. ADV# and CS# should be set up before the clock rising. During the Read command, WE# should be held in VIH. The multiple clock risings (during the low ADV# period) are allowed, but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD.
40.2 Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV# and WE# low pulse. ADV#, WE# and CS# should be set up before the clock rising. The multiple clock risings (during the low ADV# period) are allowed but, the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK ADV# Addr. CS# UB#, LB# OE# Data Out WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 40.1
0 1 2
Synchronous Burst Read
3 4 5 6 7 8 9 10 11 12 13
CLK ADV# Addr . CS# UB#, LB# WE# Data in WAIT#
Note: Latency 5, BL 4, WP: Low Enable
Figure 40.2 Synchronous Burst Write
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41 Synchronous Burst Operation Terminology
41.1 Clock (CLK)
The clock input is used as the reference for synchronous burst read and write operation of the pSRAM. The synchronous burst read and write operations are synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH.
41.2
Latency Count
The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. This value depends on the input clock frequency. Table 41.1 shows the supported Latency Count.
Table 41.1 Latency Count Support
Clock Frequency Latency Count Up to 66 MHz 5 Up to 54 MHz 4 Up to 40 MHz 3
Table 41.2
Set Latency # of Clocks for 1st data (Read) # of Clocks for 1st data (Write)
T
Number of CLocks for 1st Data
Latency 3 4 2 Latency 4 5 3 Latency 5 6 4
Clock
ADV#
Address Latency 3 Data out Latency 4 Data out Latency 5 Data out Latency 6 Data out
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
Note: The first data will always keep the Latency. From the second data on, some period of wait time may be caused by WAIT# pin.
Figure 41.1
Latency Configuration (Read)
41.3
Burst Length
Burst Length identifies how many data the device outputs during an access. The device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs to meet tBC (Burst Cycle time) parameter as 2500ns max. The first data will be output with the set Latency + tCD. From the second data on, the data will be output with tCD from each clock.
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41.4
Burst Stop
Burst stop is used when the system wants to stop burst operation on purpose. If driving CS# to VIH during the burst read operation, the burst operation is stopped. During the burst read operation, the new burst operation cannot be issued. The new burst operation can be issued only after the previous burst operation is finished. The burst stop feature is very useful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst, used mostly in the mobile handset application environment.
41.5
Wait Control (WAIT#)
The WAIT# signal is the device's output signal that indicates to the host system when it's dataout or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT# polarity (WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of WAIT# signal, the WAIT# signal should be set active one clock prior to the data regardless of Read or Write cycle.
0
CLK ADV# CS# Read Data out WAIT# Write Data in WAIT# Latency 5
1
2
3
4
5
6
7
8
9
10
11
12
13
DQ0
DQ1
DQ2
DQ3
High -Z
Latency 5 D0 D1 D2 D3
High -Z
Note: LATENCY: 5, Burst Length: 4, WP: Low Enable
Figure 41.2 WAIT# and Read/Write Latency Control
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41.6
Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in Table 41.3.
Table 41.3
Start Address 0 1 2 3 4 5 6 7
Burst Sequence
Wrap (note 1)
Burst Address Sequence (Decimal) 4 word Burst Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleave 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 word Burst Linear Interleave Linear 0-1-2-...-14-15 1-2-3-...-15-0 2-3-4-...-0-1 3-4-5-...-1-2 4-5-6-...-2-3 5-6-7-...-3-4 6-7-8-...-4-5 7-8-9-...-5-6 0-1-...-5-6-7 0-1-2-...-6-7 1-2-...-6-7-0 1-0-3-...-7-6 2-3-...-7-0-1 2-3-0-...-4-5 3-4-...-0-1-2 3-2-1-...-5-4 4-5-...-1-2-3 4-5-6-...-2-3 5-6-...-2-3-4 5-4-7-...-3-2 6-7-...-3-4-5 6-7-4-...-0-1 7-0-...-4-5-6 7-6-5-...-1-0 16 word Burst Interleave 0-1-2-3-4...14-15 1-0-3-2-5...15-14 2-3-0-1-6...12-13 3-2-1-0-7...13-12 4-5-6-7-0...10-11 5-4-7-6-1...11-10 6-7-4-5-2...8-9 7-6-5-4-3...9-8 Full Page(256 word) Linear 0-1-2-...-254-255 1-2-3-...-255-0 2-3-4-...-255-0-1 3-4-5-...-255-0-1-2 4-5-6-...-255-0-1-2-3 5-6-7-...-255-...-3-4 6-7-8-...-255-...-4-5 7-8-9-...-255-...-5-6
-
14 15
-
14-15-0-...-12-13 15-0-1-...-13-14
-
14-15-12-...-0-1 15-14-13-...-1-0
-
14-15-...-255-...-12-13 15-16-...-255-...-13-14
-
255
-
255-0-1-...-253-254
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42 Low Power Features
42.1 Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very useful tool for reducing standby current at room temperature (below 40C). DRAM cells have weak refresh characteristics in higher temperatures. High temperatures require more refresh cycles, which can lead to standby current increase. Without the internal TCSR, the refresh cycle should be set at worst condition so as to cover the high temperature (85C) refresh characteristics. But with internal TCSR, a refresh cycle below 40C can be optimized, so the standby current at room temperature can be greatly reduced. This feature is beneficial since most mobile phones are used at or below 40C in the phone standby mode.
MRS# Normal Operation MODE 0.5 s Suspend PAR mode Normal Operation
CS#
Figure 42.1 Table 42.1
Power Mode Standby (Full Array) Partial Refresh(3/4 Block) Partial Refresh(1/2 Block) Partial Refresh(1/4 Block) Address (Bottom Array) (note 2) 000000h
PAR Mode Execution and Exit PAR Mode Characteristics
Address (Top Array) (note 2) Memory Cell Data Standby Current (A, Max) 200 Valid (note 1) 170 150 140 0 Wait Time (s)
- 7FFFFFh - 5FFFFFh 000000h - 3FFFFFh 000000h - 1FFFFFh
000000h
- 7FFFFFh - 7FFFFFh 400000h - 7FFFFFh 600000h - 7FFFFFh
000000h 200000h
Notes:
1. 2. Only the data in the refreshed block are valid. The PAR Array can be selected through Mode Register Set (see Mode Register Setting Operation).
42.2 Driver Strength Optimization
The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The device supports full drive, 1/2 drive and 1/4 drive.
42.3 Partial Array Refresh (PAR) mode
The PAR mode enables the user to specify the active memory array size. The pSRAM consists of 4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays through the Mode Register Setting. The active memory array is periodically refreshed whereas the disabled array is not refreshed, so the previously stored data is lost. Even though PAR mode is enabled through the Mode Register Setting, PAR mode execution by the MRS# pin is still needed. The normal operation can be executed even in refresh-disabled array as long as the MRS# pin is not driven to the Low condition for over 0.5s. Driving the MRS# pin to the High condition puts the device back to the normal operation mode from the PAR executed mode. Refer to Figure 42.1 and Table 42.1 for PAR operation and PAR address mapping.
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43 Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Power supply voltage relative to VSS Power Dissipation Storage temperature Operating Temperature Symbol VIN , VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 2.5V 1.0 -65 to 150 -40 to 85 Unit V V W C C
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Functional operation should be restricted to use under recommended operating conditions only. Exposure to absolute maximum rating conditions longer than one second may affect reliability.
44 DC Recommended Operating Conditions
Symbol VCC VSS VIH VIL
Notes:
1. 2. 3. 4. TA=-40 to 85C, unless otherwise specified. Overshoot: VCC+1.0V in case of pulse width 20ns. Undershoot: -1.0V in case of pulse width 20ns. Overshoot and undershoot are sampled, not 100% tested.
Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage
Min 1.7 0 0.8 x VCC -0.2 (note 3)
Typ 1.85 0 -- --
Max 2.0 0 VCC + 0.2 (note 2) 0.4
Unit
V
45 Capacitance (Ta = 25C, f = 1 MHz)
Symbol CIN CIO Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min -- -- Max 8 10 Unit pF pF
Note: This parameter is sampled periodically and is not 100% tested.
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46 DC and Operating Characteristics
46.1 Common
Item Input Leakage Current Output Leakage Current Average Operating Current Output Low Voltage Output High Voltage Standby Current (CMOS) Symbol ILI ILO ICC2 VOL VOH ISB1 VIN=VSS to VCC CS#=VIH, MRS#=VIH, OE#=VIH or WE#=VIL, VIO=VSS to VCC Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS#=VIL, MRS#=VIH, VIN=VIL or VIH IOL=0.1mA IOH=-0.1mA CS# VCC-0.2V, MRS# VCC-0.2V, Other inputs = VSS to VCC < 40C < 85C 3/4 Block < 40C Partial Refresh Current MRS# 0.2V, CS# VCC-0.2V ISBP (note 1) Other inputs = VSS to VCC < 85C 1/2 Block 1/4 Block 3/4 Block 1/2 Block 1/4 Block Test Conditions Min Typ -1 -1 -- -- 1.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 1 1 40 0.2 -- TBD 200 TBD TBD TBD 170 150 140 A A Unit A A mA V V A A
Notes:
1. Full Array Partial Refresh Current (ISBP) is same as Standby Current (ISB1).
47 AC Operating Conditions
47.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC -0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load (See Figure 47.1): CL=50pF
Vtt = 0.5 x VDDQ
50 Dout Z0= 50 30pF
Figure 47.1
PAR Mode Execution and Exit
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47.2 Asynchronous AC Characteristics
(VCC=1.7-2.0V, TA=-40 to 85 C)
Symbol tRC tPC tAA tPA tCO tOE Read Cycle Time Page Read Cycle Time Address Access Time Page Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold Write Cycle Time Chip Select to End of Write ADV# Minimum Low Pulse Width Address Set-up Time to Beginning of Write Address Set-up Time to ADV# Falling Address Hold Time from ADV# Rising CS# Setup Time to ADV# Rising Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width WE# High Pulse Width Write Recovery Time WE# Low to Read Latency Data to Write Time Overlap Data Hold from Write Time Parameter Speed Bins Min 70 25 -- -- -- -- -- 10 5 5 0 0 0 3 70 60 7 0 0 7 10 60 60 55 (Note 1) 5 ns 0 1 30 0 Max -- -- 70 20 70 35 35 -- -- -- 7 7 7 -- -- -- -- -- -- -- -- -- -- -- Latency-1 clock -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- ns clock ns ns
Read
tBA tLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tWC tCW tADV tAS tAS(A) tAH(A) tCSS(A) tAW tBW tWP tWHP tWR tWLRL tDW tDH
Note: tWP (min)=70ns for continuous write operation over 50 times.
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47.3 Timing Diagrams
47.3.1 Asynchronous Read Timing Waveform
MRS# = VIH, WE# = VIH, WAIT# = High-Z
tRC
Address
tAA
CS#
tOH
tCO tCHZ
UB#, LB#
tBA tBHZ
OE#
tOE tOLZ tBLZ tLZ tOHZ Data Valid
Data out
High-Z
Notes:
1. 2. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. In asynchronous read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 47.2 Timing Waveform Of Asynchronous Read Cycle Table 47.1
Speed Symbol tRC tAA tCO tBA tOE tOH Min 70 -- -- -- -- 3 Max -- 70 70 35 35 -- Units Symbol tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Min 5 5 10 0 0 0
Asynchronous Read AC Characteristics
Speed Max -- -- -- 7 7 7 Units
ns
ns
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47.3.1.1 Page Read MRS# = VIH, WE# = VIH, WAIT# = High-Z
tRC A22~A2 tAA A1~A0
Valid Address Valid Address Valid Address Valid Address Valid Address
tOH
tCO CS# tBA UB#, LB# tOE OE# tLZ High Z tOLZ tBLZ
tPC
tBHZ
tPA
Dat a Valid Dat a Valid Dat a Valid Dat a Valid
tCHZ tOHZ
Data out
Notes:
1. 2. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. In asynchronous 4 page read cycle, Clock, ADV# and WAIT# signals are ignored.
Figure 47.3 Timing Waveform Of Page Read Cycle Table 47.2
Speed Symbol tRC tAA tPC tPA tCO tBA tOE Min 70 -- 25 -- -- -- -- Max -- 70 -- 20 70 35 35 Units Symbol tOH tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Min 3 5 5 10 0 0 0
Asynchronous Page Read AC Characteristics
Speed Max -- -- -- -- 7 7 7 Units
ns
ns
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47.3.2
Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
tWC Address tCW CS# tAW tBW tWP WE# tAS Data in High-Z tDW Dat Valid a tDH High-Z tWR
UB#, LB#
Data out
HighZ
High-Z
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
2. 3. 4. 5.
Figure 47.4 Timing Waveform Of Write Cycle Table 47.3
Symbol tWC tCW tAW tBW tWP Speed Min 70 60 60 60 55 (note 1)
Asynchronous Write AC Characteristics
Max -- -- -- -- -- Units Symbol tAS tWR tDW tDH Min 0 0 30 0 Speed Max -- -- -- -- Units
ns
ns
Note: tWP(min) = 70ns for continuous write operation over 50 times.
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47.3.2.1 Write Cycle 2 MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
tWC Address tCW CS# tAW UB#, LB# tBW tAS tWP WE# tDW Data in Dat Valid a tDH tWR
Data out
High-Z
HighZ
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
2. 3. 4. 5.
Figure 47.5 Timing Waveform of Write Cycle(2) Table 47.4
Symbol tWC tCW tAW tBW tWP
Asynchronous Write AC Characteristics (UB# & LB# Controlled)
Speed Min 70 60 60 60 55 (note 1) Max -- -- -- -- -- Units Symbol tAS tWR tDW tDH Speed Min Max 0 0 30 0 -- -- -- -- Units
ns
ns
Note: tWP(min) = 70ns for continuous write operation over 50 times.
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47.3.2.1 Write Cycle (Address Latch Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0 CLK tADV ADV# Address CS# UB#, LB# tWLRL WE# tAS Data in Read Latency 5 Data out HighZ High-Z tAS(A)
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(A) tCSS(A) tCW tAW tBW tWP tDW Dat Valid a tDH
Notes:
1. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. tCW is measured from the CS# going low to the end of write. tBW is measured from the UB# and LB# going low to the end of write. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
2. 3. 4. 5.
Figure 47.6 Timing Waveform Of Write Cycle (Address Latch Type) Table 47.5
Symbol tADV tAS(A) tAH(A) tCSS(A) tCW tAW
Notes:
1. 2. Address Latch Type, WE# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Max -- -- -- -- -- -- Units Symbol tBW tWP tWLRL tAS tDW tDH Speed Min 60 55 (note 2) 1 0 30 0 Max -- -- -- -- -- -- Units ns clock ns
Min 7 0 7 10 60 60
ns
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47.3.1
Asynchronous Write Timing Waveform in Synchronous Mode
47.3.1.1 Write Cycle (Low ADV# Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled
0 CLK ADV# tWC Address tCW CS# UB#, LB# tWLRL WE# Data in Read Latency 5 Data out High-Z HighZ tAS tDH tDW Dat Valid a tAW tBW tWP tWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Notes:
1. 2. Low ADV# type write cycle - WE# Controlled. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
3. 4. 5. 6.
Figure 47.7 Timing Waveform Of Write Cycle (Low ADV# Type) Table 47.6
Symbol tWC tCW tAW tBW tWP
Notes:
1. 2. Low ADV# Type, WE# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Max -- -- -- -- -- Units Symbol tWLRL tAS tWR tDW tDH Speed Min Max 1 -- 0 -- 0 -- 30 -- 0 -- Units clock
Min 70 60 60 60 55 (note 2)
ns
ns
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47.3.1.2 Write Cycle (Low ADV# Type) MRS# = VIH, OE# = VIH, WAIT# = High-Z, UB# & LB# Controlled
0 CLK ADV# tWC Address tCW CS# UB#, LB# WE# Data in Read Latency 5 Data out High-Z HighZ tAW tBW tAS tWLRL tWP tDH tDW Data Valid tWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Notes:
1. 2. Low ADV# type write cycle - UB# and LB# Controlled. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
3. 4. 5. 6.
Figure 47.8 Timing Waveform Of Write Cycle (Low ADV# Type) Table 47.7
Symbol tWC tCW tAW tBW tWP
Notes:
1. 2. Low ADV# type multiple write, UB#, LB# controlled. tWP(min) = 70ns for continuous write operation over 50 times.
Asynchronous Write in Synchronous Mode AC Characteristics
Max -- -- -- -- -- Units Symbol tWLRL tAS tWR tDW tDH Min 1 0 0 30 0 Speed Max -- -- -- -- -- Units clock
Speed Min 70 60 60 60 55 (note 2)
ns
ns
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47.3.1.3 Multiple Write Cycle (Low ADV# Type) MRSE = VIH, OE# = VIH, WAIT# = High-Z, WE# Controlled\
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
ADV# tWC Address tAW tCW tWR tAW tCW tWR tWC
CS#
tBW UB#, LB# tWP WE# tAS tDH tDW Data Valid High-Z tWHP tAS
tBW
tWP
Data in Data out
tDH tDW Dat Valid a High-Z
Notes:
1. 2. Low ADV# type multiple write cycle. A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS# or WE# going high. Clock input does not have any affect on the asynchronous multiple write operation if tWHP is shorter than the (Read Latency - 1) clock duration. tWP(min) = 70ns for continuous write operation over 50 times.
3. 4. 5. 6. 7.
Figure 47.9 Timing Waveform Of Multiple Write Cycle (Low ADV# Type) Table 47.8
Symbol tWC tCW tAW tBW tWP Min 70 60 60 60 55 (note 2)
Asynchronous Write in Synchronous Mode AC Characteristics
Speed Max -- -- -- -- -- ns Units Symbol tWHP tAS tWR tDW tDH Speed Min 5ns 0 0 30 0 Max Latency-1 clock -- -- -- -- ns Units --
Notes:
1. 2. Low ADV# type multiple write, WE# Controlled. tWP(min) = 70ns for continuous write operation over 50 times.
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48 AC Operating Conditions
48.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load (See Figure 48.1): CL = 30pF
Vtt = 0.5 x VDDQ
50 Dout Z0= 50 30pF
Figure 48.1
AC Output Load Circuit
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48.2 Synchronous AC Characteristics
Parameter List Clock Cycle Time Burst Cycle Time Address Set-up Time to ADV# Falling (Burst) Address Hold Time from ADV# Rising (Burst) ADV# Setup Time ADV# Hold Time CS# Setup Time to Clock Rising (Burst) Burst Operation (Common) Burst End to New ADV# Falling Burst Stop to New ADV# Falling CS# Low Hold Time from Clock CS# High Pulse Width ADV# High Pulse Width Chip Select to WAIT# Low ADV# Falling to WAIT# Low Clock to WAIT# High Chip De-select to WAIT# High-Z UB#, LB# Enable to End of Latency Clock Output Enable to End of Latency Clock UB#, LB# Valid to Low-Z Output Output Enable to Low-Z Output Burst Read Operation Latency Clock Rising Edge to Data Output Output Hold Burst End Clock to Output High-Z Chip De-select to Output High-Z Output Disable to Output High-Z UB#, LB# Disable to Output High-Z WE# Set-up Time to Command Clock WE# Hold Time from Command Clock WE# High Pulse Width UB#, LB# Set-up Time to Clock Burst Write Operation UB#, LB# Hold Time from Clock Byte Masking Set-up Time to Clock Byte Masking Hold Time from Clock Data Set-up Time to Clock Data Hold Time from Clock Symbol T tBC tAS(B) tAH(B) tADVS tADVH tCSS(B) tBEADV tBSADV tCSLH tCSHP tADHP tWL tAWL tWH tWZ tBEL tOEL tBLZ tOLZ tCD tOH tHZ tCHZ tOHZ tBHZ tWES tWEH tWHP tBS tBH tBMS tBMH tDS tDHC Speed Min 15 -- 0 7 5 7 5 7 12 7 55 -- -- -- -- -- 1 1 5 5 -- 3 -- -- -- -- 5 5 5 5 5 7 7 5 3 Max 200 2500 -- -- -- -- -- -- -- -- -- -- 10 10 12 7 -- -- -- -- 10 -- 10 7 7 7 -- -- -- -- -- -- -- -- -- ns ns clock clock ns Units
Note: 3.(VCC = 1.7-2.0V, TA=-40 to 85 C, Maximum Main Clock Frequency = 66MHz.
48.3 Timing Diagrams
48.3.1 Synchronous Burst Operation Timing Waveform
Latency = 5, Burst Length = 4 (MRS# = VIH)
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0 T CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tADVH tADVS ADV# tBEADV tAS(B) Address
Valid
tAH(B)
Don't Ca re
tBEADV
Valid
tCSS(B) CS#
tBC
Data out
Undefined
DQ0
DQ1
DQ2
DQ3
Data in
D0
D1
D2
D3
D0
Burst Command Clock
Burst Read End Clock Burst Write End Clock
Figure 48.2 Timing Waveform Of Basic Burst Operation Table 48.1
Speed Symbol T tBC tADVS tADVH Min 15 -- 5 7 Max 200 2500 -- -- Units Symbol tAS(B) tAH(B) tCSS(B) tBEADV Min 0 7 5 7
Burst Operation AC Characteristics
Speed Max -- -- -- -- Units
ns
ns
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48.3.2
Synchronous Burst Read Timing Waveforms
48.3.2.1 Read Timings Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH). CS# Toggling Consecutive Burst Read
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tBEADV tAH(B)
Don't Ca re Valid
tCSS(B) CS#
tBC
tCSHP
tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tWH tOEL tCD
Undefined
tBHZ
tOHZ tCHZ tHZ DQ2 DQ3 tWZ tWL tWH
tOH DQ0 DQ1
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge). Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 48.3 Timing Waveform of Burst Read Cycle (1) Table 48.2
Speed Symbol tCSHP tBEL tOEL tBLZ tOLZ tHZ tCHZ Min 5 1 1 5 5 -- -- Max -- -- -- -- -- 10 7 Units ns clock Symbol tOHZ tBHZ tCD tOH tWL tWH tWZ Min -- -- -- 3 -- -- --
Burst Read AC Characteristics
Speed Max 7 7 10 -- 10 12 7 Units
ns
ns
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Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH). CS# Low Holding Consecutive Burst Read
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tBEADV tAH(B)
Don't Care Valid
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tOEL
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tHZ tAWL tWH
tWH
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge). Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and address. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4. 5.
Figure 48.4 Timing Waveform of Burst Read Cycle (2) Table 48.3
Speed Symbol tBEL tOEL tBLZ tOLZ tHZ Min 1 1 5 5 -- Max -- -- -- -- 10 Units clock Symbol tCD tOH tWL tAWL tWH Min -- 3 -- -- --
Burst Read AC Characteristics
Speed Max 10 -- 10 10 12 Units
ns
ns
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Latency = 5, Burst Length = 4, WP = Low enable (WE# = VIH, MRS# = VIH). Last data sustaining
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(B)
Don't C are
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tOEL
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tWH
Notes:
1. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge). Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
2. 3.
Figure 48.5 Timing Waveform of Burst Read Cycle (3) Table 48.4
Speed Symbol tBEL tOEL tBLZ tOLZ Min 1 1 5 5 Max -- -- -- -- Units clock ns Symbol tCD tOH tWL tAWL Min -- 3 -- --
Burst Read AC Characteristics
Speed Max 10 -- 10 12 Units
ns
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48.3.2.1 Write Timings Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH). CS# Toggling Consecutive Burst Write
0 T CLK tADVH tADVS ADV# tAS(B) Address tCSS(B) CS# tBS LB#, UB# tWEH WE# tWES tDS Latency 5 Data in tWL WAIT# High-Z tWH tDHC D0 D1 D2 tDHC D3 tWZ tWL tWH Latency 5 D0 tWHP tBH tBMS tBMH
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tBEADV tAH(B)
Don't Ca re Valid
tBC
tCSHP
Notes:
1. 2. 3. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) D2 is masked by UB# and LB#. Burst Cycle Time (tBC) should not be over 2.5s.
4. 5.
Figure 48.6 Timing Waveform of Burst Write Cycle (1) Table 48.5
Speed Symbol tCSHP tBS tBH tBMS tBMH tWES tWEH Min 5 5 5 7 7 5 5 Max -- -- -- -- -- -- -- ns Units Symbol tWHP tDS tDHC tWL tWH tWZ Min 5 5 3 -- -- --
Burst Write AC Characteristics
Speed Max -- -- -- 10 12 7 ns Units
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Latency = 5, Burst Length = 4, WP = Low enable (OE# = VIH, MRS# = VIH). CS# Low Holding Consecutive Burst Write
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tBEADV tAH(B)
Don't Care Valid
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tOEL
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tHZ tAWL tWH
tWH
Notes:
1. 2. 3. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) D2 is masked by UB# and LB#. The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and address. Burst Cycle Time (tBC) should not be over 2.5s.
4. 5. 6.
Figure 48.7 Timing Waveform of Burst Write Cycle (2) Table 48.6
Symbol tBS tBH tBMS tBMH tWES tWEH Speed Min 5 5 7 7 5 5 Max -- -- -- -- -- -- ns
Burst Write AC Characteristics
Units Symbol tWHP tDS tDHC tWL tAWL tWH Speed Min 5 5 3 -- -- -- Max -- -- -- 10 10 12 ns Units
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48.3.3
Synchronous Burst Read Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(B)
Don't C are
tBSADV
Valid
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data tWL WAIT# High-Z tOEL tCD
Undefined
tCSHP tCSLH
tOH DQ0 DQ1
tCHZ
tWZ tWH HighZ
tWL
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. The burst stop operation should not be repeated for over 2.5s.
3. 4.
Figure 48.8 Timing Waveform of Burst Read Stop by CS# Table 48.7
Symbol tBSADV tCSLH tCSHP tBEL tOEL tBLZ tOLZ Speed Min 12 7 5 1 1 5 5 Max -- -- -- -- -- -- -- clock ns ns
Burst Read Stop AC Characteristics
Units Symbol tCD tOH tCHZ tWL tWH tWZ Speed Min -- 3 -- -- -- -- Max 10 -- 7 10 12 7 ns Units
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48.3.4
Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= VIH, MRS# = VIH).
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tAH(B)
Don't Ca re
tBSADV
Valid
tCSS(B) CS# tBS tCSLH tBH
tCSHP
LB#, UB#
tWEH tWES tDS Latency 5 Data in tWL WAIT# High-Z tWH D0 tDHC D1 tWZ tWL High-Z tWH Latency 5 D0 D1 D2 tWHP
WE#
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. The burst stop operation should not be repeated for over 2.5s.
3. 4.
Figure 48.9 Timing Waveform of Burst Write Stop by CS# Table 48.8
Symbol tBSADV tCSLH tCSHP tBS tBH tWES tWEH Speed Min 12 7 5 5 5 5 5 Max -- -- -- -- -- -- -- ns
Burst Write Stop AC Characteristics
Units Symbol tWHP tDS tDHC tWL tWH tWZ Speed Min 5 5 3 -- -- -- Max -- -- -- 10 12 7 ns Units
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48.3.5
Synchronous Burst Read Suspend Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (WE#= VIH, MRS# = VIH).
0 T CLK tADVH tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
1 0
11
tAH(B)
Don't Ca re
tCSS(B) CS# tBEL LB#, UB# tBLZ OE# tOLZ Latency 5 Data out tWL WAIT# High-Z tWH tOEL
tBC
tCD
Undefined
tOHZ DQ0 DQ1
tOLZ High-Z DQ1
tOH DQ2 DQ3
tHZ tWZ
Notes:
1. If the clock input is halted during burst read operation, the data output will be suspended. During the burst read suspend period, OE# high drives data output to high-Z. If the clock input is resumed, the suspended data will be output first. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) During the suspend period, OE# high drives DQ to High-Z and OE# low drives DQ to Low-Z. If OE# stays low during suspend period, the previous data will be sustained. Burst Cycle Time (tBC) should not be over 2.5s.
2.
3. 4.
Figure 48.10 Timing Waveform of Burst Read Suspend Cycle (1) Table 48.9
Symbol tBEL tOEL tBLZ tOLZ tCD tOH Speed Min 1 1 5 5 -- 3 Max -- -- -- -- 10 -- ns
Burst Read Suspend AC Characteristics
Units clock Symbol tHZ tOHZ tWL tWH tWZ Speed Min -- -- -- -- -- Max 10 7 10 12 7 ns Units
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49 Transition Timing Waveform Between Read And Write
Latency = 5, Burst Length = 4, WP = Low enable (MRS# = VIH).
0 T CLK tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21
tADVH tADV tAH(A)
tAH(B)
Don't Ca re
tBEADV tAS(A)
Valid
tCSS(B) CS#
tBC
tCSS(A) tWLRL
tAW tCW tWP
WE# tAS tOEL OE# tBEL LB#, UB# tBW tDW Data in Latency 5 Data out High -Z tWL WAIT# High-Z tWH tCD tOH
DQ0 DQ1 DQ2 DQ3
tDH
Data Valid tHZ HighZ tWZ High-Z Read Laten 5 cy
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 49.1 Table 49.1
Symbol tBEADV
Synchronous Burst Read to Asynchronous Write (Address Latch Type)
Burst Read to Asynchronous Write (Address Latch Type) AC Characteristics
Speed Min 7 Max -- Units ns Symbol tWLRL Speed Min 1 Max -- Units clock
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Latency = 5, Burst Length = 4 (MRS# = VIH).
1 T CLK tADVS ADV# tAS(B) Address
Valid
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
18 19 20 21
tADVH
tAH(B)
Don't Ca re
tBEADV
Valid Addr ss e
tCSS(B) CS# tBC
tAW tCW tWLRL
tWR
tWP
WE# tOEL
tAS
OE#
tBEL LB#, UB#
tBW tDW tDH
Data in Latency 5 Data out High-Z tWL WAIT# High-Z tWH tCD tOH
DQ0 DQ1 DQ2 DQ3
Dat Valid a tHZ High-Z
tWZ High-Z Read Late ncy 5
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 49.2 Synchronous Burst Read to Asynchronous Write (Low ADV# Type) Table 49.2
Symbol tBEADV
Burst Read to Asynchronous Write (Low ADV# Type) AC Characteristics
Speed Min 7 Max -- Units ns Symbol tWLRL Speed Min 1 Max -- Units clock
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Latency = 5, Burst Length = 4 (MRS# = VIH).
0 CLK tADVS ADV# tAS(A) Address
Valid
1
2
3
4
5
6
7
8
9
10
11 T
12 13
14 15 16 17 18 19
20
tADVH
tADV tAH(A)
Don't Ca re
tAS(B)
tAH(B)
Don't Ca re
Valid
tCSS(A) CS#
tAW tCW tWLRL
tCSS(B)
tBC
WE# tAS OE#
tWP tOEL
tBW LB#, UB# tDW Data in tDH
tBEL
Dat Valid a Latency 5 tCD tWH tOH
DQ0 DQ1 DQ2 DQ3
tHZ tWZ
Data out
HighZ Read Latency 5 HighZ
tWL
WAIT#
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 49.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing Table 49.3
Symbol tWLRL
Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
Speed Min 1 Max -- Units clock Symbol Speed Min Max Units
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Latency = 5, Burst Length = 4 (MRS# = VIH).
0 CLK tADVS tADHP ADV# tWC Address
Valid
1
2
3
4
5
6
7
8
9
10
11 T
12 13
14 15 16 17 18 19
20
tADVH
tAS(B)
tAH(B)
Don't Ca re
Valid
CS# tWLRL WE# tAS OE#
tAW tCW
tWR
tCSS(B)
tBC
tWP
tOEL
LB#, UB#
tBW tDW tDH
tBEL
Data in
Dat Valid a Latency 5 tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out
HighZ tWL tWH
tWZ
WAIT#
HighZ Read Latency 5
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 49.4 Asynchronous Write (Low ADV# Type) to Synchronous Burst Read Timing Table 49.4
Symbol tWLRL
Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed Min 1 Max -- Units clock Symbol tADHP Speed Min Max -- Units ns
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Latency = 5, Burst Length = 4 (MRS# = VIH).
0 T CLK tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21
tADVH tBEADV tAH(B)
Don't Ca re
tAS(B)
Valid
tAH(B)
tCSS(B) CS#
tBC tWES
tCSS(B)
tBC
tWEH
WE# tOEL OE# tBEL LB#, UB# Latency 5 Data in Latency 5 Data out HighZ High -Z tWL WAIT# tWH tCD High -Z tOH
DQ0 DQ1 DQ2 DQ3 D0 D1 D2
tBS tBH tDS
D3
tDHC
tHZ HighZ tWL tWH tWZ tWZ
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 49.5 Synchronous Burst Read to Synchronous Burst Write Timing Table 49.5
Symbol tBEADV
Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed Min 7 Max -- Units ns Symbol Speed Min Max Units
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Latency = 5, Burst Length = 4 (MRS# = VIH).
0 T CLK tADVS ADV# tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21
tADVH tBEADV tAH(B)
Don't Ca re
tAS(B)
Valid
tAH(B)
tCSS(B) CS# tWES WE# tWEH
tBC
tCSS(B)
tBC
tOEL OE# tBS tBH LB#, UB# Latency 5 Data in
D0 D1 D2
tBEL tDS
D3
tDHC HighZ Latency 5 tCD tWH tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out tWL WAIT# High-Z tWH
High-Z tWZ tWL
Notes:
1. 2. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. /WAIT Low (tWL or tAWL): Data not available (driven by CS# low going edge or ADV# low going edge) /WAIT High (tWH): Data available (driven by Latency-1 clock) /WAIT High-Z (tWZ): Data don't care (driven by CS# high going edge) Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising. Burst Cycle Time (tBC) should not be over 2.5s.
3. 4.
Figure 49.6 Synchronous Burst Write to Synchronous Burst Read Timing Table 49.6
Symbol tBEADV
Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Speed Min 7 Max -- Units ns Symbol Speed Min Max Units
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50 Revisions
Revision A (February 1, 2004)
Initial Release
Revision A1 (February 9, 2005)
Updated document to include Burst Speed of 66 Mhz Updated Publication Number
Revision A2 (April 11, 2005)
Updated Product Selector Guide and Ordering Information tables
Revision A3 (May 13, 2005)
Updated the entire utRAM module
Revision A4 (September 15, 2005)
Added 128-MB module.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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